• Journal of the Korea Institute of Information and Communication Engineering
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• 제12권6호
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• pp.1056-1063
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decoder is parameterized for the code rates 1/2, 1/3 and constraint lengths 7,9, thus it has four operation nodes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency. Also, the simulation results for BER (Bit Error Rate) performance show that the Viterbi decoder has BER of $10^{-4}$ at $E_b/N_o$ of 3.6 dB when it operates with code rate 1/3 and constraints 7.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제12권3호
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• pp.527-533
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• 2008

Motion compensation always produces the principal bottleneck in the real-time high quality video applications. Therefore, a fast dedicated hardware is needed to perform motion compensation in the real-time video applications. In many video encoding methods, the frames are partitioned into blocks of Pixels. In general, motion compensation predicts present block by estimating the motion from previous frame. In motion compensation, the higher pixel accuracy shows the better performance but the computing complexity is increased. In this paper, we studied an architecture of motion compensator suitable for H.264/AVC encoder that supports quarter-pixel accuracy. The designed motion compensator increases the throughput using transpose array and 3 6-tap Luma filters and efficiently reduces the memory access. The motion compensator is described in VHDL and synthesized in Xilinx ISE and verified using Modelsim_6.1i. Our motion compensator uses 36-tap filters only and performs in 640 clock-cycle per macro block. The motion compensator proposed in this paper is suitable to the areas that require the real-time video processing.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제11권8호
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• pp.1424-1433
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• 2007

In this paper, we propose a hardware architecture to generate digital hologram using the modified CGH (Computer Generated Hologram) algorithm for hardware implementation and design to FPGA (Field Programmable Gate Array) platform. After analyzing the CGH algorithm, we propose an architecture of CGH cell which efficiently products digital hologram, and design CGH Kernel from configuring CGH Cell. Finally we implement CGH Processor using CGH Kernel, SDRAM Controller, DMA, etc. Performance of the proposed hardware can be proportionally increased through simply addition of CGH Cell in CGH Kernel, since a CGH Cell has operational independency. The proposed hardware was implemented using XC2VP70 FPGA of Xilinx and was stably operated in 200MHz clock frequency. It take 0.205 second for generating $1,280{\times}1,024$ digital hologram from 3 dimensional object which has 40,000 light sources.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 한국해양정보통신학회 2009년도 추계학술대회
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• pp.393-396
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• 2009

This paper describes a design of variable-length FFT/IFFT processor for OFDM-based communication systems. The designed FFT/IFFT processor adopts the in-place single-memory architecture, and uses a hybrid structure of radix-4 and radix-2 DIF algorithms to accommodate FFT lengths of $N=64{\times}2^k$ ($0{\leq}k{\leq}7$). To achieve both memory size reduction and the improved SQNR, a two-step conditional scaling technique is devised, which conditionally scales the intermediate results of each computational stage. The performance analysis results show that the average SQNR's of 64~8,192-point FFT's are over 60-dB. The processor synthesized with a $0.35-{\mu}m$ CMOS cell library can operate with 75-MHz@3.3-V clock, and 64-point and 8,192-point FFT's can be computed in $2.55-{\mu}s$ and $762.7-{\mu}s$, respectively, thus it satisfies the specifications of wireless LAN, DMB, and DVB systems.

• Journal of IKEEE
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• 제22권4호
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• pp.886-895
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• 2018

This paper describes a hardware design of the Secure Hash Algorithm-3 (SHA-3) hash functions that are the latest version of the SHA family of standards released by NIST, and an implementation of ARM Cortex-M0 interface for security SoC applications. To achieve an optimized design, the tradeoff between hardware complexity and performance was analyzed for five hardware architectures, and the datapath of round block was determined to be 1600-bit on the basis of the analysis results. In addition, the padder with a 64-bit interface to round block was implemented in hardware. A SoC prototype that integrates the SHA-3 hash processor, Cortex-M0 and AHB interface was implemented in Cyclone-V FPGA device, and the hardware/software co-verification was carried out. The SHA-3 hash processor uses 1,672 slices of Virtex-5 FPGA and has an estimated maximum clock frequency of 289 Mhz, achieving a throughput of 5.04 Gbps.

• Journal of the Korea Institute of Information Security & Cryptology
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• 제14권5호
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• pp.37-47
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• 2004

The security of personal informations has been an important issue since the field of smart card applications has been expanded explosively. The security of smart card is based on cryptographic algorithms, which are highly required to be implemented into hardware for higher speed and stronger security. In this paper, a SEED cryptographic processor is designed by employing one round key generation block which generates 16 round keys without key registers and one round function block which is used iteratively. Both the round key generation block and the F function are using only one G function block with one 5${\times}$l MUX sequentially instead of 5 G function blocks. The proposed SEED processor has been implemented such that each round operation is divided into seven sub-rounds and each sub-round is executed per clock. Functional simulation of the proposed cryptographic processor has been executed using the test vectors which are offered by Korea Information Security Agency. In addition, we have evaluated the proposed SEED processor by executing VHDL synthesis and FPGA board test. The die area of the proposed SEED processor decreases up to approximately 40% compared with the conventional processor.

• Journal of the Korea Institute of Information Security & Cryptology
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• 제11권6호
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• pp.77-87
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• 2001

This paper describes a design of cryptographic processor that implements the Rijndael cipher algorithm, the Advanced Encryption Standard algorithm. It can execute both encryption and decryption, and supports only 128-bit block and 128-bit keys. As the processor is implemented only one round, it must iterate 11 times to perform an encryption/decryption. We implemented the ByteSub and InvByteSub transformation using the algorithm for minimizing the increase of area which is caused by different encryption and decryption. It could reduce the memory size by half than implementing, with only ROM. We estimate that the cryptographic processor consists of about 15,000 gates, 32K-bit ROM and 1408-bit RAM, and has a throughput of 1.28 Gbps at 110 MHz clock based on Samsung 0.5um CMOS standard cell library. To our knowledge, this offers more reduced memory size compared to previously reported implementations with the same performance.

• Journal of the Korea Institute of Information Security & Cryptology
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• 제14권4호
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• pp.123-134
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• 2004

In this paper a high speed architecture of the RC4 stream cipher is proposed and its FPGA implementation is presented. Compared to the conventional RC4 designs which have long initialization operation or use double or triple S-arrays to reduce latency delay due to S-array initialization phase, the proposed architecture for RC4 stream cipher eliminates the S-array initialization operation using 256-bit valid entry scheme and supports 40/128-bit key lengths with efficient modular arithmetic hardware. The proposed RC4 stream cipher is implemented using Xilinx XCV1000E-6H240C FPGA device. The designed RC4 stream cipher has about a throughput of 106 Mbits/sec at 40 MHz clock and thus can be applicable to WEP processor and RC4 key search processor.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제23권11호
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• pp.1377-1383
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• 2019

Histogram equalization is the most frequently used algorithm for image enhancement. Its hardware implementation significantly outperforms in time its software version. The overall performance of FPGA-based implementation of histogram equalization can be improved by applying pipelining in the design and by exploiting the multipliers and a lot of SRAM blocks which are embedded in recent FPGAs. This work proposes how to implement a fast histogram equalization circuit for 8-bit gray level images. The proposed design contains a FIFO to perform equalization on an image while the histogram for next image is being calculated. Because of some overlap in time for histogram equalization, embedded multipliers and pipelined design, the proposed design can perform histogram equalization on a pixel nearly at a clock. And its dual parallel version outperforms in time almost two times over the original one.

• Journal of Advanced Navigation Technology
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• 제24권6호
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• pp.533-539
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• 2020

Real-time service (RTS) provided by IGS provides correction for GNSS orbit and clock via internet, so it is widely used in fields that require real-time precise positioning. However, the RTS signal may be lost due to an unstable Internet environment. When signal disconnection occurs, signal prediction can be performed using polynomial models. However, the RTS changes rapidly after the GNSS navigation message issue of data (IOD) changes, so it is difficult to predict when signal loss occurs at that point. In this study, we proposed an algorithm to generate continuous RTS correction information by applying the difference in navigation trajectory according to IOD change. The use of this algorithm can improve the accuracy of RTS prediction at IOD changes. After performing optimization studies to improve RTS prediction performance, the predicted RTS trajectory information was applied to precision positioning (PPP). Compared to the conventional method, the position error is significantly reduced, and the error increase along with the signal loss interval increase is reduced.