• Journal of IKEEE
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• v.22 no.2
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• pp.233-241
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• 2018

This paper describes a lightweight implementation of a cryptographic processor supporting GCM (Galois/Counter Mode) authenticated encryption (AE) that is based on the two block cipher algorithms of ARIA and AES. It also provides five modes of operation (ECB, CBC, OFB, CFB, CTR) for confidentiality as well as the key lengths of 128-bit and 256-bit. The ARIA and AES are integrated into a single hardware structure, which is based on their algorithm characteristics, and a $128{\times}12-b$ partially parallel GF (Galois field) multiplier is adopted to efficiently perform concurrent processing of CTR encryption and GHASH operation to achieve overall performance optimization. The hardware operation of the ARIA/AES-GCM AE processor was verified by FPGA implementation, and it occupied 60,800 gate equivalents (GEs) with a 180 nm CMOS cell library. The estimated throughput with the maximum clock frequency of 95 MHz are 1,105 Mbps and 810 Mbps in AES mode, 935 Mbps and 715 Mbps in ARIA mode, and 138~184 Mbps in GCM AE mode according to the key length.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.1
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• pp.69-77
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• 1989

A hologram scanner for POS bar code symb9ol readers has been developed. This system is composed of scanning optics, optical detector, video signal circuitary and preprocessor. In contrast to conventional scanners using polygonal mirrors, which complicate the scanning optics, the hologram scanner developed in this research was made up with simple optics and higher reading performance was achieved. And in order to read abar code symbol omnidirectionally with highdensity scan patterns, the new real time decoding technique was proposed. The advantage of this technique is less hardware and lower clock rate. High speed processing and improved readability for tilted symbol was confirmed experimentally.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.20-26
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• 1999

A CMOS 6-bit 100MSPS ADC for DBS receiver is designed. The proposed ADC is composed of folding block, latch block, and digital block. The cascode interpolating block and kickback reduced latch are proposed with a high speed architecture. To verify the performance of ADC, simulations are carried out by HSPICE. The ADC achieves a clock frequency of 100MHz with a power dissipation of 40mW for 3 V supply voltage. The active chip area is $1500{\mu}m{\times}1000{\mu}m$with $0.65{\mu}m$ 2-poly 2-metal CMOS process. Further, INL and DNL are within ${\pm}0.6LSB$, ${\pm}0.5LSB$, respectively. SNDR is about 33dB at 10MHz input frequency.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.47-58
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• 1999

As the performance of processors improves, cache memories are used to overcome the difference of speed between processors and main memories. Generally cache memories are embedded and small sizes, fault coverage is a more important factor than test time in testing point of view. A new test algorithm and a new BIST architecture are developed to detect various fault models with a relatively small overhead. The new concurrent BIST architecture uses the comparator of cache management blocks as response analyzers for tag memories. A modified scan-chain is used for pre-testing of comparators which can reduce test clock cycles. In addition several boundary scan instructions are provided to control the internal test circuitries. The results show that the new algorithm can detect SAFs, AFs, TFs linked with CFs, CFins, CFids, SCFs, CFdyns and DRFs models with O(12N), where N is the memory size and the new BIST architecture has lower overhead than traditional architecture by about 11%.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.6
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• pp.279-283
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• 2012

In is paper, we design and implement the low power, high speed touch screen controller that calculates and outputs the coordinate of touch point on the touch screen of mobile devices. The system clock is 10HMz, the number of input channels is 21, standby current is $20{\mu}A$, dynamic range of input is 140pF~400pF and the response time is 0.1ms/frame. It contains the power management unit for low power, automatic impedance calibration unit in order to adapt to humidity, temperature and evaluation board, adjacent key and pattern interference suppression unit, serial interface unit of I2C and SPI. The function and performance is verified by using FPGA and $0.18{\mu}m$ CMOS standard process. The implemented touch screen is designed for using in the double layer ITO(Indium Thin Oxide) module with diamond pattern and single layer ITO module for cost-effective which are applied to mobile phone or smart remote controller.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.85-94
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• 2003

The asynchronous design methods proved to have the higher performance in power consumption and execution speed than synchronous ones because it just needs to activate the required module without feeding clock in the system. Despite the advantage of CISC machine providing the variable addressing modes and instructions, its execution scheme is hardly suited for a synchronous Pipeline architecture and incurs a lot of overhead. This paper proposes a novel asynchronous pipeline architecture, A80sl, whose instruction set is fully compatible with that of Intel 80C51, an embedded micro controller. We classify the instructions into the group keeping the same execution scheme for the asynchronous pipeline and optimize it eliminating the bubble stage that comes from the overhead of the multi-cycle execution. The new methodologies for branch and various instruction lengths are suggested to minimize the number of states required for instructions execution and to increase its parallelism. The proposed A80C51 architecture is synthesized with 0.35${\mu}{\textrm}{m}$ CMOS standard cell library. The simulation results show higher speed than that of Intel 80C51 with 36 MHz and other asynchronous counterparts by 24 times.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.7-16
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• 2000

This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It performed the division and square-toot by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.2
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• pp.37-44
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• 2004

In this paper, we performed the design and the development of the wide-band correlation board to be an important role in the autocorrelation spectrometer's building for the observation study of an extra-galaxy's spectral lines and the survey research of the special radio sources in field of the radio astronomy. In this research, the developed correlation board by using QUAINT correlator chip(made by NRAO) has maximum 100 MHz clock speed and operate at a intermediate frequency with 400 MHz bandwidth. For the Performance test we supply the 0.5 and 1.67 MHz rectangular wave, then we obtain the autocorrelation coefficients. The final results, which process by using FFT, get the almost same results compare with the theoretical correlation.

• The Journal of the Korea Contents Association
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• v.13 no.11
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• pp.541-550
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• 2013

Generally in case of tablet PC's, the Windows 8 is used to support various functions or development convenience, however it cannot support real-time processing. In addition, existing commercial solutions and RTiK has a problem to support real-time processing due to impossibility of getting APIC timer count value which is used to generate timer interrupt separated from that of Windows. Thus, in this paper, we set the initial APIC count value using MSR_FSB_FREQ to support real-time processing on the Windows 8-based tablet PC's. Additionally, we deal with designing and implementing RTiK+ providing real-time processing to guarantee interrupt periods by controlling C-State which is used for low power techniques. To evaluate the performance of the proposed RTiK+, we measured the periods of generated real-time threads using RDTSC instructions which return the number of CPU clock ticks, and verified that RTiK+ operates correctly within the error ranges of 1ms.

• Journal of Korea Multimedia Society
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• v.16 no.4
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• pp.483-492
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• 2013

SURF is an algorithm which extracts feature points and generates their descriptors from input images, and it is being used for many applications such as object recognition, tracking, and constructing panorama pictures. Although SURF is known to be robust to changes of scale, rotation, and view points, it is hard to implement it in real time due to its complex and repetitive computations. Using 3.3 GHz Pentium, in our experiment, it takes 240ms to extract feature points and create descriptors in a VGA image containing about 1,000 feature points, which means that software implementation cannot meet the real time requirement, especially in embedded systems. In this paper, we present a hardware architecture that can compute the SURF algorithm very fast while consuming minimum hardware resources. Two key concepts of our architecture are parallelism (for repetitive computations) and efficient line memory usage (obtained by analyzing memory access patterns). As a result of FPGA synthesis using Xilinx Virtex5LX330, it occupies 101,348 LUTs and 1,367 KB on-chip memory, giving performance of 30 frames per second at 100 MHz clock.