• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.96-103
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• 2006

This paper proposes a new technique for improving the efficiency of single phase high frequency switch mode boost converter. This converter includes an additional boost converter that follows the main hish frequency switching device. The additional converter, which is controlled at lower frequencies, bypasses almost all the current in the main switch and the high frequency switching loss is greatly reduced. Both switching devices are controlled by a simple method; each controller consists of a one-shot multivibrator, a comparator and an AND gate, and the maximum switching frequency can be limited without any clock generator. The converter works cooperatively in high efficiency and acts as though it were a conventional high frequency switch mode converter with one switching device. This paper describes the proposed converter configuration, design, and discusses the steady state performance concerning the switching loss reduction and efficiency improvement. and the proposed method is verified by computer simulation.

• Journal of Korea Multimedia Society
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• v.15 no.1
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• pp.81-86
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• 2012

This paper presents a VLSI design for lifting-based discrete wavelet transform (DWT) 9/7 filter using multiplierless multiple constant multiplication (MCM) architecture. This proposed design is based on the lifting scheme using pattern search for folded architecture. Shift-add operation is adopted to optimize the multiplication process. The conventional serial operations of the lifting data flow can be optimized into parallel ones by employing paralleling and pipelining techniques. This optimized design has simple hardware architecture and requires less computation without performance degradation. Furthermore, hardware utilization reaches 100%, and the number of registers required is significantly reduced. To compare our work with previous methods, we implemented the architecture using Verilog HDL. We also executed simulation based on the logic synthesis using $0.18{\mu}m$ CMOS standard cells. The proposed architecture shows hardware reduction of up to 60.1% and 44.1% respectively at 200 MHz clock compared to previous works. This implementation results indicate that the proposed design performs efficiently in hardware cost, area, and power consumption.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.7B
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• pp.1081-1090
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• 2010

$0.18{\mu}m$ CMOS UHF RFID tag frontend is presented in this paper. Several key components are highlighted: the voltage multiplier based on the threshold voltage terminated circuit, the demodulator using current mode, and the clock generator. For standard compliance, all designed components are under the EPC Global Class-1 Generation-2 UHF RFID protocol. Backscatter modulation uses the pulse width modulation scheme. Overall performance of the proposed tag chip was verified with the evaluation board. Prototype Tag Chip dimension is neary 0.77mm2 ; According to the simulation results, the reader can successfully interrogate the tag within 1.5m. where the tag consumes the power about $71{\mu}W$.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1749-1753
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• 2003

We proposed several systems for 1Giga bit Modem. The first, Binary ASK(Amplitude Shift Keying) system has a high speed shutter transmitter and no IF(Intermediate Frequency) receiver only by symbol synchronization. The advantage of proposed system is that circuitry is very simple without IF process. The disadvantage of proposed system are that line spectrum occurs interference to other channels, and enhancement to 4-level system is impossible due to its large SNR degradation. The second, Binary phase modulation system has a high speed shutter transmitter and IF-VCO(IF-Voltage Controlled Oscillator) control by base-band phase rotation. Polarity of shutter window is changed by the binary data. The window should be narrow same as above ASK. The advantage of proposed system is which error rate performance is superior. The disadvantage of proposed system are that Circuitry is more complex, narrow pull-in range of receiver caused by VCO and spectrum divergence by the non-linear amplifier. The third, 4-QAM(Quadrature Amplitude Modulation)system has a nyquist pulse transmitter and IF-VCO control by symbol clock. The advantage of proposed system are that signal frequency band is a half of 1GHz, reliable pull-in of VCO and possibility of double speed transmission(2Gbps) by keeping 1GHz frequency-band. The disadvantage of proposed system are that circuit complexity of pulse shaping and spectrum divergence by the non-linear amplifier.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.8 s.338
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• pp.11-16
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• 2005

This paper proposes a bit manipulation accelerator (BMA) having application specific instructions, which efficiently supports scrambling, convolutional encoding, puncturing, and interleaving. Conventional DSPs cannot effectively perform bit manipulation functions since かey have multiply accumulate (MAC) oriented data paths and word-based functions. However, the proposed accelerator can efficiently process bit manipulation functions using parallel shift and Exclusive-OR (XOR) operations and bit jnsertion/extraction operations on multiple data. The proposed BMA has been modeled by VHDL and synthesized using the SEC $0.18\mu m$ standard cell library and the gate count of the BMA is only about 1,700 gates. Performance comparisons show that the number of clock cycles can be reduced about $40\%\sim80\%$ for scrambling, convolutional encoding and interleaving compared with existing DSPs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.45-51
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• 2003

In this paper, a scan-based low power BIST (Built-In Self-Test) architecture is proposed. The proposed architecture is based on STUMPS, which uses a LFSR (Linear Feedback Shift Register) as the test generator, a MISR(Multiple Input Shift Register) as the reponse compactor, and SRL(Shift Register Latch) channels as multiple scan paths. In the proposed BIST a degenerate MISR structure is used for every SRL channel; this offers reduced area overheads and has less impact on performance than the STUMPS techniques. The proposed BIST is designed to support both test-per-clock and test-per-scan techniques, and in test-per-scan the total power consumption of the circuit can be reduced dramatically by suppressing the effects of scan data on the circuits. Results of the experiments on ISCAS 89 benchmark circuits show that this architecture is also suitable for detecting path delay faults, when the hamming distance of the data in the SRL channel is considered.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.378-386
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• 2017

A return-to-zero (RZ) digital-to-analog converter (DAC) with a tri-state switching scheme is proposed in this paper. The proposed scheme provides a triple weight output for RZ operation by using a conventional differential current switch and simple pseudo-differential F/Fs. The RZ function is realized with only two additional transistors in each F/F cell, which results in a power dissipation increase of less than 5%. To verify the performance of the proposed method, a 10-bit RZ DAC is fabricated using standard 180-nm CMOS technology. Measured results show that the worst SFDR performances are 60 dBc and 55 dBc in the 1st and 2nd Nyquist bands, respectively, when operating at 650 MHz clock frequency. The total power consumption is 64 mW, and the active area occupies $0.25mm^2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.6
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• pp.1075-1082
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• 2017

This paper describes a design of hash processor which can execute new hash algorithm, SHA-3 and extendable-output function (XOF), SHAKE-256. The processor that consists of padder block, round-core block and output block maximizes its performance by using the block-level pipelining scheme. The padder block formats the variable-length input data into multiple blocks and then round block generates SHA-3 message digest or SHAKE256 result for multiple blocks using on-the-fly round constant generator. The output block finally transfers the result to host processor. The hash processor that is implemented with Xilinx Virtex-5 FPGA can operate up to 220-MHz clock frequency. The estimated maximum throughput is 5.28 Gbps(giga bits per second) for SHA3-512. Because the processor supports both SHA-3 hash algorithm and SHAKE256 algorithm, it can be applicable to cryptographic areas such as data integrity, key generation and random number generation.

• Physical Therapy Rehabilitation Science
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• v.6 no.3
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• pp.134-139
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• 2017

Objective: Dual-task interference is defined as decrements in performance observed when people attempt to perform two tasks concurrently, such as a verbal task and walking. The purpose of this study was to investigate the changes of gait ability according to the dual task interference in chronic stroke survivors. Design: Cross-sectional study. Methods: Ten chronic stroke survivors (9 male, 1 female; mean age, 55.30 years; mini mental state examination, 19.60; onset duration, 56.90 months) recruited from the local community participated in this study. Gait ability (velocity, paretic side step, and stride time and length) under the single- and dual-task conditions at a self-selected comfortable walking speed was measured using the motion analysis system. In the dual task conditions, subjects performed three types of cognitive tasks (controlled oral word association test, auditory clock test, and counting backwards) while walking on the track. Results: For velocity, step and stride length, there was a significant decrease in the dual-task walking condition compared to the single walking condition (p<0.05). In particular, higher reduction of walking ability was observed when applying the counting backward task. Conclusions: Our results revealed that the addition of cognitive tasks while walking may lead to decrements of gait ability in stroke survivors. In particular, the difficulty level was the highest for the calculating task. We believe that these results provide basic information for improvements in gait ability and may be useful in gait training to prevent falls after a stroke incident.

• Journal of Environmental Science International
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• v.27 no.8
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• pp.723-735
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• 2018

In this study, to investigate an optimal configuration method for the modeling system, we performed an optimization experiment by controlling the types of compilers and libraries, and the number of CPU cores because it was important to provide reliable model data very quickly for the national air quality forecast. We were made up the optimization experiment of twelve according to compilers (PGI and Intel), MPIs (mvapich-2.0, mvapich-2.2, and mpich-3.2) and NetCDF (NetCDF-3.6.3 and NetCDF-4.1.3) and performed wall clock time measurement for the WRF and CMAQ models based on the built computing resources. In the result of the experiment according to the compiler and library type, the performance of the WRF (30 min 30 s) and CMAQ (47 min 22 s) was best when the combination of Intel complier, mavapich-2.0, and NetCDF-3.6.3 was applied. Additionally, in a result of optimization by the number of CPU cores, the WRF model was best performed with 140 cores (five calculation servers), and the CMAQ model with 120 cores (five calculation servers). While the WRF model demonstrated obvious differences depending on the number of CPU cores rather than the types of compilers and libraries, CMAQ model demonstrated the biggest differences on the combination of compilers and libraries.