• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.6
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• pp.1009-1018
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• 2017

We developed new Digital Sampler for KVN(: Korean VLBI Network). The sampler has 1024MHz sampling frequency with 2bits/sample. The sampler's input reference frequencies are 1pps(: pulse per second) and 10MHz, also UTC(: Universal Time Coordinated) time information out with 1PPS signal, synchronized. The output of sampling data is adapted VSI(: VLBI Standard Interface) specification including the time information. In order to confirm the performance of the sampler, we carried out the astronomical radio observation test in Ulsan Radio Observatory of KVN. It was confirmed the stable performance. In this paper, We introduce the new developed sampler and present the observational test result.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.12
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• pp.3029-3034
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• 2014

The paper describes the scleral diagnostic system implementation for human eyes by using the scleral color code and vessels sign pattern code generations. The system is based on the high performance DSP image signal processor, programmable gain control for preprocessing and RISC SD frames storage. RGB image signals are optimized by PGC, the edge image is detected form the gray image converted. The processing algorithms are executed by scleral color code generation and scleral vessels sign pattern code creation for discriminating and matching. The scleral symptomatic color code is generated by YCbCr values at memory map tolerated and the vessel sign pattern code is created by digitizing the 24 clock and 13 ring zones, overlay matching and tolerances. The experimental results for performance are that the system runs 40ms, and the color and pattern for diagnostic errors are around 20% and 24% on average. The system and technique enable a scleral diagnosis with subdividing the patterns and patient database.

• The Transactions of the Korea Information Processing Society
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• v.1 no.4
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• pp.479-489
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• 1994

At the present time, it is an important problem that we are to select a transmission line code for the very-high speed optical transmission system which can confidentially transfer the original information signal sequence efficiently, as it is to be the large capacity and the economization for the optical digital transmission system to transfer the information signal sequence at the very-high speed. Therefore, this paper is to select first the proper transmission line codes for the high speed(more than Mb/s) optical transmission system of the proposed two-level unipolar transmission line codes up to date, and to decide a mBIZ (m Binary with One Zero insertion) code as an optimal transmission line code for the very-high speed optical transmission system, resulting from analyzing the performance at the requirements of the transmission line code, such as the maximum consecutive identical digits, the transmission delay time, the increasing rate of clock, the mark rate, the circuit complexity, the supervision of transmission line error, and power spectrum among the selected transmission line codes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.54-58
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• 2007

Development of high performance LTPS TFTs contributed to open up new SOP technology with various digital circuits integrated in display panels. This work introduces the current mode logic(CML) gate design method with which one can replace slow CMOS logic gates. The CML inverter exhibited small logic swing, fast response with high power consumption. But the power consumption became compatible with CMOS gates at higher clock speed. Due to small current values in CML, layout area is smaller than the CMOS counterpart even though CML uses larger number of devices. CML exhibited higher noise immunity thanks to its non-inverting and inverting outputs. Multi-input NAND/AND and NOR/OR gates were implemented by the same circuit architecture with different input confirugation. Same holds for MUX and XNOR/XOR CML gates. We concluded that the CML gates can be designed with few simple circuits and they can improve power consumption, chip area, and speed of operation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.5
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• pp.1103-1108
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• 2010

In this paper, Frequency Synthesizer which is widely used for FH-SS system is proposed and the experimental results are analyzed. The performance of the DPLL(Digital Phase-Locked-Loop), which is the main part of the Synthesizer is analyzed by the computer program. Using Maxplus-II tool provided by altera. co., ltd, each part of the DPLL is designed and all of them is integrated into EPM7064SLC44-10 chip. And the simulation results are compared with the characteristics of the implemented circuits for analysis. And the experiential results show that the N value of the loop filter is toggled to adjacent N value, which result in phase jitter of the output. It can be resolved by increasing DCO(Digital Controlled oscillator) clock rate.

• The KIPS Transactions:PartA
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• v.16A no.5
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• pp.347-356
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• 2009

Precise branch prediction is a critical factor in the IPC Improvement of modern microprocessor architectures. In addition to the branch prediction accuracy, branch prediction delay have a profound impact on overall system performance as well. However, it tends to be overlooked when the architects design the branch predictor. To tolerate branch prediction delay, this paper proposes Early Start Prediction (ESP) technique. The proposed solution dynamically identifies the start instruction of basic block, called as Basic Block Start Address (BB_SA), and the solution uses BB_SA when predicting the branch direction, instead of branch instruction address itself. The performance of the proposed scheme can be further improved by combining short interval hiding technique between BB_SA and branch instruction. The simulation result shows that the proposed solution hides prediction latency, with providing same level of prediction accuracy compared to the conventional predictors. Furthermore, the combination with short interval hiding technique provides a substantial IPC improvement of up to 10.1%, and the IPC is actually same with ideal branch predictor, regardless of branch predictor configurations, such as clock frequency, delay model, and PHT size.

• The KIPS Transactions:PartC
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• v.15C no.1
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• pp.31-36
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• 2008

The clock frequency difference of sensor nodes is one of main parameters in TOF estimation and affect to degrade ranging algorithms to estimate positions of mobile nodes in wireless sensor networks. The specification of IEEE802.15.4a describes asynchronous TWR and SDS-TWR insensitive to frequency difference without any additional network synchronization. But the TWR and SDS-TWR can not eliminate sufficiently the effect of frequency difference of node pair, packet processing delay and its difference. Especially use of low cost oscillator with wide range offset, sensor node with different hardware and software can make the positioning errors worse. We propose an estimation method of frequency differences, and apply the measured frequency differences to TWR and SDS-TWR. We evaluate the performance of the proposed algorithm with simulation, and make certain that the proposed method enhances the performance of existing algorithms with positioning errors less than 25 cm.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.11
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• pp.801-805
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• 2009

Hardware based dynamic voltage and frequency scaling is a promising technique to reduce power consumption in a globally asynchronous locally synchronous system such as a homogeneous or heterogeneous multi-core system. In this paper, FPGA prototype design of hardware based dynamic frequency scaling is proposed. The proposed techniques are applied to a FIFO based multi-core system for a software defined radio and Network-on-Chip based hardware MPEG2 encoder. Compared with a references system using a single global clock, the first prototype design reduces the power consumption by 78%, but decreases the performance by 5.9%. The second prototype design shows that power consumption decreases by 29.1% while performance decreases by 0.36%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.7
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• pp.875-880
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• 2019

A RC4 stream cipher is widely used for security applications such as IEEE 802.11 WEP, IEEE 802.11i TKIP and so on, because it can be simply implemented to dedicated circuits and achieve a high-speed encryption. RC4 is also used for systems with limited resources like IoT, but there are performance limitations. RC4 consists of two stages, KSA and PRGA. KSA performs initialization and randomization of S-box and K-box and PRGA produces cipher texts using the randomized S-box. In this paper, we initialize the S-box and K-box in the randomization of the KSA stage to reduce the initialization delay. In the randomization, we use clusters to process swap operation between elements of S-box in parallel and can generate two cipher texts per clock. The proposed RC4 cipher hardware can initialize S-box and K-box without any delay and achieves about 2 times to 6 times improvement in KSA randomization and key stream generation.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.1
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• pp.27-32
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• 2019

This study describes the design and implementation of a simulated signal generator to demonstrate the performance of VHF band radar for the detection of small targets in RCS(Radar Cross Section). The transmission and reception antenna beam widths used in the simulated signal generating apparatus may be large, which may cause problems in the degree of isolation. Interference signal immunity and isolation characteristics are improved by considering operating conditions of VHF radar to solve isolation of antennas. Simulated signal generator performs the following: VHF radar transmission and reception correction, simulation signal generation, target Doppler, RCS and distance simulation, remote control, and GPS clock synchronization function. After the fabrication of the simulated signal generator, the main characteristics, such as the output characteristics and the reflection signal simulations, were tested. When the microwave radar assembly is completed in the future, it will be utilized for the performance evaluation of VHF radar.