• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.191-196
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• 2005

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver has been designed and implemented. It consists of a clock recovery circuit, a RF mixer and frequency discriminator for phase/frequency detection, a DR-VCO, a phase shifter, and a hold circuit. The recovered 40 GHz clock is synchronized with a stable 10 GHz DR-VCO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module has shown to significantly improve the performance of the conventional open-loop type clock recovery module with DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When input signal is dropped, the 40 GHz clock is generated continuously by hold circuit. The implemented clock recovery module can be used as a low-cost and high-performance receiver module for 40 Gb/s commercial optical network.

• The KIPS Transactions:PartC
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• v.11C no.1
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• pp.123-134
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• 2004

The synchronized clock performance in the synchronization network and SDH transmission network design is an important element in aspect of guaranteeing network stability and data transmission. Consequently the simulator which can applicable various parameters and several input levels from the best state to the worst state for performance analysis of the synchronized clock is required in case of network design. Therefore, in this paper, 1 developed the SNCA and TNCA for analysis of the synchronized clock in the synchronization network and transmission network. And utilizing these simulators with various wander generation, node number and clock state, 1 obtained the synchronized clock characteristics and maximum network nodes In NE1, NE2 and NE3 transmission network and DOTS1, DOTS2 synchronization network.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.394-397
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• 2003

In this paper, we have proposed a clock recovery algorithm of OFDM/QPSK-DMR(Orthogonal Frequency Division Multiplexing/Quadrature Phase Shift Keying Modulation-Digital Microwave Radio)system using BL-PSF(Band Limited-Pulse Shaping Filter) and have analyzed the clock phase error variance performance of OFDM/QPSK and single carrier DMR systems. The existing OFDM/QPSK-DMR system using the windowing requires training sequence or CP(Cyclic Prefix) to synchronize a receiver clock frequency Because there is no training sequence or CP(Cyclic prefix) in our proposed DMR system, the proposed clock recovery algorithm is useful to the OFDM/QPSK-DMR system using BL-PSF, The simulation results confirm that the proposed clock recovery algorithm has the same clock phase error variance performance in a single carrier DMR system under AWGN(Additive White Gaussian Noise) environment.

• The KIPS Transactions:PartC
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• v.16C no.5
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• pp.637-644
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• 2009

A study about performance analysis of synchronization clock using measured clock noises is required. Therefore this paper executed the study for performance analysis of synchronization clock and acquirement of maximum number of network node with various clock states using measured clock noises in NG-SDH networks. Also this paper generated a suitable clock model using measured clock noises, and carried out simulations with various clock states. Through the simulation results, maximum numbers were 80 or more network nodes in normal state, and were below 37 nodes in short-term phase transient(SPT) state, and were 50 or more in long-term phase transient(LPT) state. Accordingly this study showed that maximum numbers to meet ITU-T specification were below 37 network nodes in three clock states. Also this study showed that when SPT or LPT states occur from NE network before DOTS system, synchronization source must change with other stable synchronization source of normal state.

• Earthquakes and Structures
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• v.7 no.2
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• pp.217-231
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• 2014

Ancient masonry towers are regarded as among the most important historical heritage structures of the world. These slender structures typically have orthogonal and circular geometry in plane. These structural forms are commonly installed with adjacent structures. Because of their geometrical shapes and structural constraints, ancient masonry towers are more vulnerable to earthquake damage. The main goal of the paper is to investigate the seismic behavior of Erzurum Clock Tower under earthquake loading and to determine the contribution of the castle walls to the seismic performance of the tower. In this study, four three-dimensional finite element models of the Erzurum Clock Tower were developed and the seismic responses of the models were investigated. Time history analyses were performed using the earthquakes that took place in Turkey in 1983 near Erzurum and in 1992 near Erzincan. In the first model, the clock tower was modeled without the adjacent walls; in the second model, the clock tower was modeled with a castle wall on the south side; in the third model, the clock tower was modeled with a castle wall on the north side; and in the last model, the clock tower was modeled with two castle walls on both the north and south sides. Results of the analyses show that the adjacent walls do not allow lateral movements and the horizontal displacements decreases. It is concluded that the adjacent structures should be taken into consideration when modeling seismic performance in order to get accurate and realistic results.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.2
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• pp.83-87
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• 2011

Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. Almost systems require that the clock length is required prior to scheduling, the best value of the clock can be found only after evaluating different schedules. In this study, we presents a scheduling method that works simultaneously with synthesis by selecting a clock from a chainable operation set. Our scheduling algorithm is based on list scheduling and executes chaining considering bit level delays based on selected clock period. Experimental results show that our method improves the performance by 18 percent.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.391-393
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• 2004

For performance and stability of a synchronized system, we need an efficient Clock Tree Synthesis(CTS) methodology to design clock distribution networks. In a system-on-a-chip(SOC) design environment, CTS effectively distributes clock signals from clock sources to synchronized points on layout design. In this paper, we suggest the pre-layout analysis of the clock network including gated clock, multiple clock, and test mode CTS optimization. This analysis can help to avoid design failure with potential CTS problems from logic designers and supply layout constraints so as to get an optimal clock distribution network. Our new design flow including pre-layout CTS analysis and structural violation checking also contributes to reduce design time significantly.

• Journal of Positioning, Navigation, and Timing
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• v.5 no.3
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• pp.137-144
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• 2016

In this paper, the performance of ranging measurement, which is generated using two receiver clock offsets in one receiver, was analyzed. A spoofer transmits a counterfeited spoofing signal which is similar to the GPS signal with hostile purposes, so the same tracking technique can be applied to the spoofing signal. The multi-correlator can generate two receiver clock offsets in one receiver. The difference between these two clock offsets consists of the path length from the spoofer to the receiver and the delay of spoofer system. Thus, in this paper, the ranging measurement was evaluated by the spoofer localization performance based on the time-of-arrival (TOA) technique. The results of simulation and real-world experiments show that the position and the system clock offset of the spoofer could be estimated successfully.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37C no.10
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• pp.894-900
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• 2012

Indoor wireless positioning system uses ranging information of beacons in order to precisely estimate a tag location. To estimate distance between each beacons and tag, the system calculates arrival time of a tag pulse with clock of each beacon including independent clock offset. This clock offset seriously affects the performance of ranging and positioning. We propose in this paper a clock offset compensation method to solve this problem. To verify the performance of the proposed method, we simulated location estimation with random clock offset between -1,000ppm and 1,000ppm, and the result shows that the proposed scheme effectively solves the clock offset problem.

• Journal of information and communication convergence engineering
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• v.6 no.4
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• pp.383-390
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• 2008

Clock skew modeling is important in the performance evaluation and prediction of clock distribution network and it is one of the major constraints for high-speed operation of synchronous integrated circuits. In clock routing synthesis, it is necessary to reduce the clock skew under the specified skew bound, while minimizing the cost such as total wire length and delay. In this paper, a new efficient bounded clock skew routing method is described, which generalizes the well-known bounded skew tree method by allowing loops, i.e., link-edges can be inserted to a clock tree when they are beneficial to reduce the clock skew and/or the wire length. Furthermore, routing topology construction and wire sizing is used to reduce clock delay.