• Journal of the Microelectronics and Packaging Society
• /
• v.24 no.3
• /
• pp.1-6
• /
• 2017

As the performance and density of IC devices increase, especially the clock frequency increases, power grid network integrity problems become more challenging. To resolve these power integrity problems, the use of passive devices such as resistor, inductor, and capacitor is very important. To manage the power integrity with little noise or ripple, decoupling capacitors are essential in electronic packaging. The decoupling capacitors are classified into voltage regulator capacitor, board capacitor, package capacitor, and on-chip capacitor. For next generation packaging technologies such as 3D packaging or wafer level packaging on-chip MIM decoupling capacitor is the key element for power distribution and delivery management. This paper reviews the use and necessity of on-chip decoupling capacitor.

• Journal of Institute of Control, Robotics and Systems
• /
• v.6 no.2
• /
• pp.228-233
• /
• 2000

It is common to apply the technology of FPGA (Fie이 Programmable Gate Array) which is one of the design methods for ASIC(Application Specific IC)to the active components used in the data processing at the digital system of satellite aircraft missile etc for compact lightness and integration of Printed Circuit Board (PCB) In carrying out the digital data processing the FPGAs are designed for the various functions of the Process Control Interrupt Control Clock Generation Error Detection and Correction (EDAC) as the individual module. In this paper an FPGA chip for Single Error Correction and Double Error Detection (SEC-DED) for EDAC is designed and simulated by using a VLSI design software LODECAP.

• Journal of Power Electronics
• /
• v.10 no.3
• /
• pp.228-234
• /
• 2010

This paper investigates the conducted-noise characteristics of a digitally-controlled randomly-switched dc-dc converter. In order to investigate the effect of the suggested digital controller on the conducted-noise characteristics of a dc-dc converter, three factors have been studied: the field-programmable gate array (FPGA) clock speed, the randomization ratio percentage, and the effect of using a closed loop feedback controller. A field-programmable gate array is much more flexible than analog control circuits, has a lower cost, and can be used for power supply applications. A novel FPGA-based implementation has been suggested for obtaining the experimental validations and realizing the studied concepts. Furthermore, the experimental results have been discussed and design guidelines have been included.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.7
• /
• pp.81-88
• /
• 2002

A new pattern generator of BIST based on the pattern clustering is developed. The proposed technique embeds a pre-computed deterministic test set with low hardware overhead for test-per-clock environments. The test control logic is simple and can be synthesized automatically. Experimental results for the ISCAS benchmark circuits show that the effectiveness of the new pattern generator compared to the previous methods.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.11 no.6
• /
• pp.353-359
• /
• 2016

In this paper, we propose a high performance L1 cache structure for the high clock CPU. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to reduce miss ratio, and a way-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is stored into the two-way set associative buffer. For the high performance and fast access time, we propose an one way among two ways set associative buffer is selectively accessed based on the way-select table (WST). According to simulation results, access time can be reduced by about 7% and 40% comparing with a direct cache and Intel i7-6700 with two times more space respectively.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.53-56
• /
• 2001

With the ever increasing clock frequency and integration level of CMOS circuits, I/O(input/output) and interconnect issues are becoming a growing concern. In this thesis, we propose the 2.5Gbps high speed input driver This driver consists of four different blocks, which are the high speed serializer , PECL(pseudo emitter coupled logic) Line Driver, PLL(phase lock loop) and pre-emphasis signal generator. The proposed pre-emphasis block will compensate the high frequency components of the 2.5Gbps data signal. Using the pre-emphasis block, we can obtain 2.5Gbps data signal with differential peak to peak voltage about 900 m $V_{p.p}$ This driver structure is on fabrication in 2.5v/10.25um 1poly, 5metal CMOS process.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.955-958
• /
• 1999

We designed a phase locked loop (PLL), which is applicable to microprocessor clock generation application. The designed PLL has a new simple phase frequency detector (PFD) which eliminate dead-zone and has a good high frequency characteristic. The lock-in range of the designed PLL is 50 MHz ~ 150 MHz at 3.3v power supply voltage. The design is carried out using a 0.6${\mu}{\textrm}{m}$ triple metal CMOS process. The area of the layout is 0.35mm by 0.42mm with 359 transistors.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.11 no.2
• /
• pp.117-123
• /
• 2016

In general, PCM (Phase Change Memory) is unsuitable as a main memory because it has limitations: high read/write latency and low endurance. However, the DRAM&PCM hybrid memory with the same level is one of the effective structures for a next generation main memory because it can utilize an advantage of both DRAM and PCM. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an access time and write count of PCM by using an effective page replacement. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM access count by around 60% and the PCM write count by 42% given the same PCM size, compared with Clock-DWF algorithm.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.64 no.7
• /
• pp.1026-1030
• /
• 2015

In this paper, we propose a signal processing board of an optical delay simulator for evaluating a long-range laser range finder and a laser target designator. We improved the accuracy by applying the clock multiplication and the correction of error gradient. To evaluate the performance of the proposed method, we implemented a prototype board and performed experiments. As a result, we implemented the optical delay simulator with resolution less than 0.7m in measuring distance 60km and a standard deviation of 0.041m. The PRF code detection logic and generation logic have a stability less than 0.03% and 0.08% compared to the NATO standard, respectively.

• Journal of Sensor Science and Technology
• /
• v.21 no.5
• /
• pp.389-393
• /
• 2012

A chaotic oscillator with light controllability was designed. The proposed chaotic oscillator consists of a photo sensor, two phase clock driven MOS switches, nonlinear function blocks for chaotic signal generation. SPICE circuit analysis using a 0.35 um CMOS process parameters was performed for its chaotic dynamics. And we confirmed that chaotic behaviors of the circuit can be controlled according to light intensity. By SPICE simulation, chaotic dynamics by time waveforms, frequency analysis was analyzed. SPICE results showed that proposed circuit can make various light-controlled chaotic signals.