• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.48-55
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• 2017

This paper proposes a new link structure that transmits power, clock, and data through a single optical fiber for a future automotive network. A pulse-position modulation (PPM) technique is adopted to guarantee a DC-balanced signal for robust power transmission regardless of transmitted data pattern. Further, circuit implementations and theoretical analyses for the proposed PPM transceiver are described in this paper. A prototype transceiver fabricated in 65-nm CMOS technology, is used to verify the PPM signaling part of the proposed system. The prototype achieves a $10^{-13}$ bit-error rate and 0.188-UI high frequency jitter tolerance while consuming 14 mW at 800 Mb/s.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.101-101
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• 2000

MSC(Multispectral Camera), which will be a unique payload on KOMPSAT-II, is designed to collect panchromatic and multi-spectral imagery with a ground sample distance of 1m and a swath width of 15km at 685km altitude in sun-synchronous orbit. The instrument is designed to have an orbit operation duty cycle of 20% over the mission life time of 3 years. MSC electronics consists of three main subsystems; PMU(Payload Management Unit), CEU(Camera Electronics Unit) and PDTS(Payload Data Transmission Subsystem). PMU performs all the interface between spacecraft and MSC, and manages all the other subsystems by sending commands to them and receiving telemetry from them with software protocol through RS-422 interface. CEU controls FPA(Focal Plane Assembly) which contains TDI(Timc Delay Integration) CCD(Charge Coupled Device) and its clock drivers. PMU provides a Master Clock to synchronize panchromatic and multispectral camera. PDTS performs compression, storage and encryption of image data and transmits them to the ground station through x-band.

• ETRI Journal
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• v.26 no.6
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• pp.653-656
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• 2004

This paper presents an effective algorithm for inserting an MPEG-2 transport stream (TS) into a Digital Audio Broadcasting (DAB) ensemble without any bandwidth waste in a Digital Multimedia Broadcasting (DMB) transmission system. The key technologies of this algorithm include packet rate control and program clock reference correction, which are important for TS processing. The proposed algorithms are applied to the various DMB transmission systems based on Eureka-147, and the performance of the proposed algorithm is confirmed through the experimental DMB broadcasting.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.133.3-133
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• 2001

This paper analyses the real-time performance of Ethernet based intranet whether it is applicable to the real-time network. Unpredictability of transmission delay by collision-delay-retransmission mechanism in CAMA/CD(Carrier Sense Multiple Access with Collision Detect) of Ethernet is the major reason making hard to apply to real-time system. Both retransmission mechanism of TCP(Transmission Control Protocol) for reliability and sliding windows algorithm for high utilization make hard to predict transmission delay. Because real-time control network require fast responsibility and bustle of short-periodic messages, global-clock for collision avoidance and UDP(User Datagram Protocol) for high utilization of network are used. The mathematical models for time-delay that can be occured between ...

• Journal of Communications and Networks
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• v.8 no.3
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• pp.351-359
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• 2006

In this article, we present a new slow-start variant, which improves the throughput of transmission control protocol (TCP) Vegas. We call this new mechanism Gallop-Vegas because it quickly ramps up to the available bandwidth and reduces the burstiness during the slow-start phase. TCP is known to send bursts of packets during its slow-start phase due to the fast window increase and the ACK-clock based transmission. This phenomenon causes TCP Vegas to change from slow-start phase to congestion-avoidance phase too early in the large bandwidth-delay product (BDP) links. Therefore, in Gallop-Vegas, we increase the congestion window size with a rate between exponential growth and linear growth during slow-start phase. Our analysis, simulation results, and measurements on the Internet show that Gallop-Vegas significantly improves the performance of a connection, especially during the slow-start phase. Furthermore, it is implementation feasible because only sending part needs to be modified.

• Korean Journal of Optics and Photonics
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• v.13 no.4
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• pp.295-300
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• 2002

We developed an optical transmitter and receiver for an electrical time division multiplexed (ETDM) 20 Gb/s optical transmission system, and experimentally investigated their characteristics. Especially, the clock extraction circuit, which is a key component in realizing broadband optical transmission receivers, was realized by using an NRZ-to-PRZ converter implemented with a half-period delay line and an EX-OR, a high-Q bandpass filter using a cylindrical dielectric resonator, and a microstrip coupled-line bandpass filter. Finally, the bit-error-rate of demultiplexed 10 Gb/s electrical signal after back to-back transmission was measured, and a high receiver sensitivity [-26.2 dBm for NRZ ($2^{7}-1$) pseudorandom binary sequence (PRBS)] was obtained

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.4 no.2
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• pp.29-36
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• 2005

All-optical fiber-type $2{\times}32$ splitters for an Ethernet PON (passive optical network) were fabricated by using a FBT (fiber biconical tapered) process and the performance of the splitters was tested in upstream transmission of the EPON system. The $2{\times}32$ splitters was obtained by cascading $1{\times}4$ splitters fabricated by a conventional FBT process and showed -18 dB of insertion loss with 1.5 dB uniformity of output power at each channel and -0.1 dB of polarization dependent loss. The insertion loss variation was below 0.1 dB at the temperature range of $-40^{\circ}C\;to\;80^{\circ}C$. For upstream channel transmission test in the EPON system were a Zig board and a burst mode receiver. Zenko-made optical module was used for the burst mode receiver by adding functions of serializer/deserializer and clock data recovery, a Virtex II pro20 chipset and Vitesse VSC7123 were used in the Zig board for characterizing the burst mode and in the clock data recovery chipset, respectively. Startup acquisition lock time and data acquisition lock time were measured to be 670ns and 400ns, respectively, in the upstream channel transmission of the EPON system adapting the $2{\times}32$ splitter fabricated in this work.

• The Transactions of the Korea Information Processing Society
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• v.1 no.4
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• pp.479-489
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• 1994

At the present time, it is an important problem that we are to select a transmission line code for the very-high speed optical transmission system which can confidentially transfer the original information signal sequence efficiently, as it is to be the large capacity and the economization for the optical digital transmission system to transfer the information signal sequence at the very-high speed. Therefore, this paper is to select first the proper transmission line codes for the high speed(more than Mb/s) optical transmission system of the proposed two-level unipolar transmission line codes up to date, and to decide a mBIZ (m Binary with One Zero insertion) code as an optimal transmission line code for the very-high speed optical transmission system, resulting from analyzing the performance at the requirements of the transmission line code, such as the maximum consecutive identical digits, the transmission delay time, the increasing rate of clock, the mark rate, the circuit complexity, the supervision of transmission line error, and power spectrum among the selected transmission line codes.

• Journal of IKEEE
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• v.13 no.2
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• pp.118-125
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• 2009

With recent advancement of high-speed, multi-gigabit data transmission capabilities, transmitters usually send data without clock signals for reduction of hardware complexity, power consumption, and cost. Therefore clock and data recovery circuits(CDR) become important to recover the clock and data signals and have been widely studied. This paper presents the design of 10Gbps CDR in 0.18$\mu$m CMOS process. A quarter-rate bang-bang phase detector is designed to reduce the power and circuit complexity, and a 4-stage LC-type VCO is used to improve the jitter characteristics. Simulation results show that the designed CDR consumes 80mW from a 1.8V supply, and exhibits a peak-to-peak jitter of 2.2ps in the recovered clock. The chip layout area excluding pads is 1.26mm$\times$1.05mm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.34-43
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• 2008

An OpenLDI receiver circuit for flat-panel display systems was designed and fabricated using $1.8-{\mu}m$ high-voltage CMOS technology. Designed circuit roughly consists of DLL circuit and parallelizers, which recovers clock and parallelize data bits, respectably. It has one clock input and four data inputs. Measurement results showed that it successfully recovers clock signal from input whose frequency is $10Mhz{\sim}65Mhz$, which corresponds data rate of $70Mbps{\sim}455Mbps$ per channel, or $280Mbps{\sim}1.82Gbps$ when all of the four data channels were utilized. A commercial LCD monitor was modified into a test-bench and used for video data transmission at clock frequency of 49Mhz. In the experiment, power consumption was 19mW for core block and 82.5mW for output buffer.