• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.54-61
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• 1999

This paper describes the design of a 4-Mbps wireless infrared data transceiver chip. The receiver consits of the analog front-end, clock recovery and frame generator, and demodulator. The transmitter consists of the demodulator and LED driver. The versatile analog front- end consisting of multiple amplifiers makes it possible for the chip to be applied to various infrared environments by compensating DC and offset signal components. A 4PPM (pulse position modulation) scheme is used for data transfer in order to meet the IrDA standards. The chip was fabricated in a $0.8-{\mu}m$ 2-poly, 2-metal CMOS technology and dissipates 122mW for ${\pm}2.5V$ supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6A
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• pp.871-880
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• 1999

In this paper, a pseudo-noise(PN) tracking and demodulation circuits are analyzed and designed for a direct-sequence/spread-spectrum multiple access system under a mobile fading channel. We consider noncoherent delay locked loop(DLL) as a PN code tracking loop which has 1/8 PN chip resolution. The tracking performance of DLL is evaluated in terms of locking time from a loose state and tracking jitter. The received signal is demodulated to original data by despreading with PN code locked by DLL. Also the designed circuit supports sound service of 32Kbps and in-band signal with 4.096MHz chip clock. The circuits are implemented and verified with FPGA, which is shown completely data recovery under AWGN 7dB and will be available for IMT-2000.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.11-20
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• 1998

High-speed complex-number arithmetic units are essential to baseband signal processing of modern digital communication systems such as channel equalization, timing recovery, modulation and demodulation. In this paper, a new complex-number multiplication algorithm is proposed, which is based on redundant binary (RB) arithmetic combined with radix-4 Booth recoding scheme. The proposed algorithm reduces the number of partial product by one-half as compared with the conventional direct method using real-number multipliers and adders. It also leads to a highly parallel architecture and simplified circuit, resulting in high-speed operation and low power dissipation. To demonstrate the proposed algorithm, a prototype complex-number multiplier-accumulator (CMAC) core with 10-bit operands has been designed using 0.8-$\mu\textrm{m}$ N-Well CMOS technology. The designed CMAC core contains about 18,000 transistors on the area of about 1.60 ${\times}$ 1.93 $\textrm{mm}^2$. The functional and speed test results show that it can operate with 120-MHz clock at V$\sub$DD/=3.3-V, and its power consumption is given to about 63-mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12A
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• pp.2000-2011
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• 2001

In this Paper, we convert conventional low speed(1x, 6x) DVD systems designed by analog PLL(Phase Locked Loop) into digital PLL to operate at high speed systems flexibly, and present optimal DPLL model in high speed(20x) DVD systems. Especially, we focused on the design of DPLL that can overcome channel effects such as bulk delay, sampling clock frequency offset and asymmetry phenomenon in high speed DVD systems. First, the modified Early-Late timing error detector as digital timing recovery scheme is proposed. And the four-sampled compensation algorithm using zero crossing point as asymmetry compensator is designed to achieve high speed operation and strong reliability. We show that the proposed timing recovery algorithm provides enhanced performances in jitter valiance and SNR margin by 4 times and 3dB respectively. Also, the new four-sampled zero crossing asymmetry compensation algorithm provides 34% improvement of jitter performance, 50% reduction of compensation time and 2.0dB gain of SNR compared with other algorithms. Finally, the proposed systems combined with asymmetry compensator and DPLL are shown to provide improved performance of about 0.4dB, 2dB over the existing schemes by BER evaluation.

• Journal of Korean Society of Forest Science
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• v.38 no.1
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• pp.27-32
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• 1978

The diurnal pattern of leaf water potential in cuttings by Dye Method was as follows: 1. Diurnal pattern of leaf water potential (${\psi}_l$) in Viburnum Awabuki K. Koch and Daphne odora Thunb. was shown the pattern of the curves without mutual relation with soil classes when soil water potential (${\psi}_s$) was 0 bar. When ${\psi}_s$ was above -0.01 bar, the cuttings in the loamy sand (L.S.) was shown by the maximum values than that in sandy clay (S.C.) by about -1 bar gap (Fig. 1). 2. The diurnal changes of ${\psi}_l$ was shown the most high from two to eight O'clock in the morning, the maximum value was -3 bars when ${\psi}_s$ was above -0.01 to -0.02 bar, and was -4 bars below -0.03 bar. The diurnal the lowest values of ${\psi}_l$ showed -20 to -22 bars from one to two O'clock in the afternoon. In the fifteenth day after cutting V.A., the staying time in the diurnal maximum values of ${\psi}_l$ is about half in comparison with it in the fifth day. The curves of recovery of water stress (Fig. 1), the former reached to the diurnal maximum values -1 to -2 bars lately every hours comparing with it of the latter. The general diurnal pattern of ${\psi}_l$ was most clearly related to change with air temperature and the relative humitidy. 3. Comparing the treatment block by IAA 50 ppm with controlled block in fifteenth day after V.A. cuttings, in case of treatment reached to maximum values -2 to -3 bars lately as shown Fig. 2., and also staying times was only half in comparison with controlled block. 4. The cuttings 4 leafs was much rootings than 2 leafs in V.A. (Table. 1), and the former reached maximum value -2 to -3 bars lately every hours comparing with the latter. 5. In case of Buxus microphylla var. Koreana as shown Fig. 3., comparing the pattern curves of in the cuttings 8 leafs with 4 leafs, the former reached to maximum values -2 to -3 bars lately in comparison with the latter, but reffering to the amount of rooting (Table. 2), the former is less than the latter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.50-55
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• 2008

In this paper, New LC VCO with $8{\sim}10.9$ GHz Band has been designed using commercial $0.35-{\mu}m$ CMOS technology. This proposed circuit is consisted of the parallel construction of the typical NMOS and PMOS cross-coupled pair which is based on the LC tank, MOS cross-coupled pair which has same tail current of complementary NMOS and PMOS, and output buffer. The designed LC VCO, which is according to proposed structure in this paper, takes a 29% improvement of the wide tuning range as 8 GHz to 10.9 GHz, and a 6.48mW of low power dissipation. Its core size is $270{\mu}m{\times}340{\mu}m$ and its phase noise is as -117dBc Hz and -137dBc Hz at 1-MHz and 10-MHz offset, respectively. FOM of the new proposed LC VCO gets -189dBc/Hz at a 1-MHz offset from a 10GHz center frequency. This design is very useful for the 10Gb/s clock generator and data recovery integrated circuit(IC) and SONET communication applications.