• 한국산업정보학회논문지
• /
• 제18권5호
• /
• pp.9-14
• /
• 2013

본 논문은 DLL 기술을 사용하여서 낮은 위상잡음을 갖는 주파수 체배기를 설계 하였다. VCDL은 공통모드 잡음을 줄이기 위해서 차동구조를 이용하여 설계 되었다. 이번 설계는 65nm, 1.2V TSMC CMOS 공정을 이용 하였고, 동작 주파수 범위는 10MHz에서 24MHz로 측정되었다. TCXO를 기준 주파수로 사용하여 위상잡음을 측정하였을 때 38.4MHz의 출력에서 1MHz offset 기준으로 -125dBc/Hz가 측정되었다. 총 면적은 $0.032mm^2$을 사용하였고, 출력 버퍼를 포함하여 총 1.8mA의 전류를 칩에서 소비하였다.

• 전기학회논문지P
• /
• 제55권1호
• /
• pp.26-30
• /
• 2006

For the purpose of developing capacitive humidity sensor having interdigital electrodes, interdigital electrode was modeled and simulated to obtain capacitance and sensitivity as a function of geometric parameters like the structural gap and thickness. For the development of ASIC, switched capacitor signal processing circuits for capacitive humidity sensor were designed and simulated by Cadence using $0.25{\mu}m$ CMOS process parameters. The signal processing circuits are composed of amplifier for voltage gain control, and clock generator for sensor driving and switch control. The characteristics of the fabricated sensors are; 1) sensitivity is 9fF/%R.H., 2) temperature coefficient of offset(TCO) is $0.4%R.H./^{\circ}C$, 3) nonlinearity is 1.2%FS, 4) hysteresis is 1.5%FS in humidity range of $3%R.H.{\sim}98%R.H.$. The response time is 50 seconds in adsorption and 70 seconds in desorption. Fabricated process used in this capacitive humidity sensor having interdigital electrode are just as similar as conventional IC process technology. Therefore this can be easily mass produced with low cost, simple circuit and utilized in many applications for both industrial and environmental measurement and control system, such as monitoring system of environment, automobile, displayer, IC process room, and laboratory etc.

• International Journal of Precision Engineering and Manufacturing
• /
• 제8권4호
• /
• pp.22-26
• /
• 2007

We describe a new way of implementing absolute displacement measurements by exploiting the optical comb of a femtosecond pulse laser as a wavelength ruler, The optical comb is stabilized by locking both the repetition rate and the carrier offset frequency to an Rb clock of frequency standard. Multiwavelength interferometry is then performed using the quasi-monochromatic beams of well-defined generated wavelengths by tuning an external cavity laser diode consecutively to preselected light modes of the optical comb. This scheme of wavelength synthesizing allows the measurement of absolute distances with a high precision that is traceable to the definition of time. The achievable wavelength uncertainty is $1.9{\times}10^{-10}$, which allows the absolute heights of gauge blocks to be determined with an overall calibration uncertainty of 15 nm (k = 1). These results demonstrate a successful industrial application of an optical frequency synthesis employing a femtosecond laser, a technique that offers many possibilities for performing precision length metrology that is traceable to the well-defined international definition of time.

• Journal of Astronomy and Space Sciences
• /
• 제34권1호
• /
• pp.19-30
• /
• 2017

The optical wide-field patrol network (OWL-Net) is a Korean optical surveillance system that tracks and monitors domestic satellites. In this study, a batch least squares algorithm was developed for optical measurements and verified by Monte Carlo simulation and covariance analysis. Potential error sources of OWL-Net, such as noise, bias, and clock errors, were analyzed. There is a linear relation between the estimation accuracy and the noise level, and the accuracy significantly depends on the declination bias. In addition, the time-tagging error significantly degrades the observation accuracy, while the time-synchronization offset corresponds to the orbital motion. The Cartesian state vector and measurement bias were determined using the OWL-Net tracking data of the KOMPSAT-1 and Cryosat-2 satellites. The comparison with known orbital information based on two-line elements (TLE) and the consolidated prediction format (CPF) shows that the orbit determination accuracy is similar to that of TLE. Furthermore, the precision and accuracy of OWL-Net observation data were determined to be tens of arcsec and sub-degree level, respectively.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제16권5호
• /
• pp.675-681
• /
• 2016

A 41dB gain control range $6^{th}$-order band-pass receiver front-end (RFE) using CMOS switched frequency translated impedance (FTI) is presented in a 40 nm CMOS technology. The RFE consists of a frequency tunable RF band-pass filter (BPF), IQ gm cells, and IQ TIAs. The RF BPF has wide gain control range preserving constant filter Q and pass band flatness due to proposed pre-distortion scheme. Also, the RF filter using CMOS switches in FTI blocks shows low clock leakage to signal nodes, and results in low common mode noise and stable operation. The baseband IQ signals are generated by combining baseband Gm cells which receives 8-phase signal outputs down-converted at last stage of FTIs in the RF BPF. The measured results of the RFE show 36.4 dB gain and 6.3 dB NF at maximum gain mode. The pass-band IIP3 and out-band IIP3@20 MHz offset are -10 dBm and +12.6 dBm at maximum gain mode, and +14 dBm and +20.5 dBm at minimum gain mode, respectively. With a 1.2 V power supply, the current consumption of the overall RFE is 40 mA at 500 MHz carrier frequency.

• 대한전자공학회논문지TC
• /
• 제37권1호
• /
• pp.88-97
• /
• 2000

초고속이면서 소요 메모리의 크기를 극소화한 IP 라우터용 Lookup 알고리즘을 제안하고 성능을 분석하였다. 메모리 크기가 작으므로 고속/고가의 SRAM(10ns)을 사용할 수 있고, 구조가 간단하여 하드웨어로 구현 가능하였다. 본 장치는 1${\sim}$3회의 메모리 접근을 통해 Lookup이 가능하고, IPMA 사이트에서 구한 40,000개의 라우팅 정보를 이용하여 시뮬레이션한 결과 대략 ${\sim}$316KB의 포워딩 테이블용 메모리만이 소요된다. 이때 압축을 수행하는 옵셋 임계치는 8이다. ALTERA EPM7256시리즈에 100MHz 클럭을 이용하여 모사시험한 결과 10ns 접근속도를 가진 SRAM 기준으로 2회의 메모리 접근만으로 Lookup하는 경우 45ns의 접근시간이 소요되며, 3회의 메모리 접근이 필요한 경우는 ${\sim}$177ns의 접근시간이 소요된다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제7권4호
• /
• pp.267-273
• /
• 2007

A fractional-N frequency synthesizer supports quadruple bands and multiple standards for mobile broadcasting systems. A novel linearized coarse tuned VCO adopting a pseudo-exponential capacitor bank structure is proposed to cover the wide bandwidth of 65%. The proposed technique successfully reduces the variations of KVCO and per-code frequency step by 3.2 and 2.7 times, respectively. For the divider and prescaler circuits, TSPC (true single-phase clock) logic is extensively utilized for high speed operation, low power consumption, and small silicon area. Implemented in $0.18-{\mu}m$ CMOS, the PLL covers $154{\sim}303$ MHz (VHF-III), $462{\sim}911$ MHz (UHF), and $1441{\sim}1887$ MHz (L1, L2) with two VCO's while dissipating 23 mA from 1.8 V supply. The integrated phase noise is 0.598 and 0.812 degree for the integer-N and fractional-N modes, respectively, at 750 MHz output frequency. The in-band noise at 10 kHz offset is -96 dBc/Hz for the integer-N mode and degraded only by 3 dB for the fractional-N mode.

• 대한전기학회논문지:전기물성ㆍ응용부문C
• /
• 제50권3호
• /
• pp.144-148
• /
• 2001

For the purpose of developing capacitive humidity sensor having interdigit electrodes, interdigit electrode was modeled and simulated to obtain capacitance and sensitivity as a function of geometric parameters like the structural gap and thichness. For the development of ASIC, switched capacitor signal conditioning circuits for capacitive humidity sensor were designed and simulated by cadence using 0.25um CMOS process parameters. The signal conditioning circuits are composed of amplifier for voltage gain control, and clock generator for sensor driving and switch control The characteristics of the fabricated sensors are; 1) sensitivity is 9fF/%R.H., 2) temperature coefficient of offset(TCO) is 0.4%R.H./$^{\circ}C$, 3) nonlinearity is 1.2%FS, 4) hysteresis is 1.5%FS in humidity range of 3%R.H. ${\sim}$ 98%R.H.. The response time is 50 seconds in adsorption and 70 seconds in desorption. Fabricated process used in this capacitive humidity sensor having interdigit electrode are just as similar as conventional IC process technology. Therefore this can be easily mass produced with low cost, simple circuit and utilized in many applications for both industrial and environmental measurement and control system, such as monitoring system of environment, automobile, displayer, IC process room, and laboratory etc..

• 한국통신학회논문지
• /
• 제28권2A호
• /
• pp.96-101
• /
• 2003

본 연구는wideband code division multiple access (WCDMA) 단말기 복조기의 주요 구성 요소인 time tracker의 구현과 설계 parameter 설정에 관한 것이다. Time tracker는 2차 feedback loop로 구성되었고 모의실험을 통하여time error detector (TED)의 이득을 기지국이 송출하는 전체 전력에서 CPICH 전력이 차지하는 비의 함수로 도출하였다. Loop filter, numerically controlled oscillator (NCO) 설계를 포함한 time tracker의 전달함수를 구하였다. 모의실험을 통하여 기지국과 단말 사이의 clock time offset, loop bandwidth를 매개변수로 하여 DPCH 전력에 따른 bit error rate (BER)를 구하였고 이를 근거로 통신 환경에 따라 설정해 주어야 할 적합한 이득 값을 제시하였다.

• 한국군사과학기술학회지
• /
• 제19권3호
• /
• pp.379-386
• /
• 2016

In this paper, phase noise analysis result for 2.4 GHz PLL(phase locked loop) using SPD(sample phase detector) is proposed. It can be used for high performance frequency synthesizer's LO(local oscillator) to extend output frequency range or for LO of offset PLL to reduce a division rate or for clock signal of DDS(direct digital synthesizer). Before manufacturing, theoretical estimation of PLL's phase noise performance should be performed. In order to calculate phase noise of PLL using SPD, Leeson model is used for modeling phase noise of VCO(voltage controlled oscillator) and OCXO(ovened crystal oscillator). After theoretically analyzing phase noise of PLL, optimized loop filter bandwidth was determined. And then, phase noise of designed loop filter was calculated to find suitable OP-Amp. Also, the calculated result of phase noise was compared with the measured one. The measured phase noise of PLL was -130 dBc/Hz @ 10 kHz.