• Proceedings of the Korean Information Science Society Conference
• /
• 2010.06b
• /
• pp.324-327
• /
• 2010

최근 카메라 센서는 ISP(Image Signal Processor)를 별도로 사용하지 않고 SOC(System on Chip) 방식으로 설계를 하여 소형화를 추구하고 있지만, High Resolution의 카메라가 개발 요구되어지면서 센서 Pixel 및 스위칭 트랜지스터의 집적화가 심화되고 있다. 이러한 고집적화는 카메라 센서 내 발열 관리에 대한 관심을 높여주고 있다. 본 논문에서는 우선 SOC 센서가 ISP를 탑재한 센서이므로 프로세서 발열 관리 기법에 대해 먼저 소개를 한 후, SOC 방식 센서를 대상으로 열이 발생되는 관련 조건을 확인 검사하고, 분석한 결과를 보인다. 또한 이러한 분석 결과를 토대로 발열을 제어 할 수 있는 방법으로 DAC(Digital Analog Converter)를 사용하여 센서 내 사용되는 전류 증폭을 최소화 한 설계 방식에 대해 분석해 보았으며, 전류 증폭을 최소화한 결과 최대 PCLK(Pixel Clock)에서도 열화에 따른 Noise(Hot Pixel)를 개선시킬 수 있었다.

• Journal of Astronomy and Space Sciences
• /
• v.36 no.3
• /
• pp.169-180
• /
• 2019

In this study, a batch least square estimator that utilizes optical observation data is developed and utilized to determine geostationary orbits (GEO). Through numerical simulations, the effects of error sources, such as clock errors, measurement noise, and the a priori state error, are analyzed. The actual optical tracking data of a GEO satellite, the Communication, Ocean and Meteorological Satellite (COMS), provided by the optical wide-field patrol network (OWL-Net) is used with the developed batch filter for orbit determination. The accuracy of the determined orbit is evaluated by comparison with two-line elements (TLE) and confirmed as proper for the continuous monitoring of GEO objects. Also, the measurement residuals are converged to several arcseconds, corresponding to the OWL-Net performance. Based on these analyses, it is verified that the independent operation of electro-optic space surveillance systems is possible, and the ephemerides of space objects can be obtained.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.8 no.1
• /
• pp.9-18
• /
• 2008

Recently according to the development of an information society the information technology equipments which a clock frequency has the facility over a number giga hertz have been developed much. And we have research which leakage electromagnetic signals can use at the communication security and tapping. In this paper, we restored leakage electromagnetic signals of the monitors. And we proposed efficient recovery technique to restore the screen of the monitor. First of all, we understand a screen characteristic of the monitor. And then we restored a monitor screen from leakage electromagnetic signals from the monitor. For also we tried to use a Wavelet transform and filters to remove the noise for better performance. In the result of the experiment, we used leakage electromagnetic signals and confirmed the possibility of a monitor screen of the recovery. And we improve the performance with Wavelet transform and filters.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.3
• /
• pp.404-416
• /
• 2015

Small-area, low-power coarse and fine frequency detectors (FDs) are proposed for an adaptive bandwidth referenceless CDR with a wide range of input data rate. The coarse FD implemented with two flip-flops eliminates harmonic locking as long as the initial frequency of the CDR is lower than the target frequency. The fine FD samples the incoming input data by using half-rate four phase clocks, while the conventional rotational FD samples the full-rate clock signal by the incoming input data. The fine FD uses only a half number of flip-flops compared to the rotational FD by sharing the sampling and retiming circuitry with PLL. The proposed CDR chip in a 65-nm CMOS process satisfies the jitter tolerance specifications of both USB 3.0 and USB 3.1. The proposed CDR works in the range of input data rate; 2 Gb/s ~ 8 Gb/s at 1.2 V, 4 Gb/s ~ 11 Gb/s at 1.5 V. It consumes 26 mW at 5 Gb/s and 1.2 V, and 41 mW at 10 Gb/s and 1.5 V. The measured phase noise was -97.76 dBc/Hz at the 1 MHz frequency offset from the center frequency of 2.5 GHz. The measured rms jitter was 5.0 ps at 5 Gb/s and 4.5 ps at 10 Gb/s.

• IEIE Transactions on Smart Processing and Computing
• /
• v.4 no.5
• /
• pp.371-378
• /
• 2015

In this paper, a different type of pulse width modulation (PWM) control scheme for a buck converter is introduced. The proposed buck converter uses PWM with frequency hopping and a low quiescent.current low dropout (LDO) voltage regulator with a power supply rejection ratio enhancer to reduce high spurs, harmonics and output voltage ripples. The low quiescent.current LDO voltage regulator is not described in this paper. A three-bit binary-to-thermometer decoder scheme and voltage ripple controller (VRC) is implemented to achieve low voltage ripple less than 3mV to increase the efficiency of the buck converter. An internal clock that is synchronized to the internal switching frequency is used to set the hopping rate. A center frequency of 2.5MHz was chosen because of the bluetooth low energy (BLE) application. This proposed DC-DC buck converter is available for low-current noise-sensitive loads such as BLE and radio frequency loads in portable communications devices. Thus, a high-efficiency and low-voltage ripple is required. This results in a less than 2% drop in the regulator's efficiency, and a less than 3mV voltage ripple, with -26 dBm peak spur reduction operating in the buck converter.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
• /
• v.2
• /
• pp.385-390
• /
• 2006

This paper examines the sampling and jitter specifications and considerations for Global Navigation Satellite Systems (GNSS) software receivers. Software radio (SWR) technologies are being used in the implementation of communication receivers in general and GNSS receivers in particular. With the advent of new GPS signals, and a range of new Galileo and GLONASS signals soon becoming available, GNSS is an application where SWR and software-defined radio (SDR) are likely to have an impact. The sampling process is critical for SWR receivers, where it occurs as close to the antenna as possible. One way to achieve this is by BandPass Sampling (BPS), which is an undersampling technique that exploits aliasing to perform downconversion. BPS enables removal of the IF stage in the radio receiver. The sampling frequency is a very important factor since it influences both receiver performance and implementation efficiency. However, the design of BPS can result in degradation of Signal-to-Noise Ratio (SNR) due to the out-of-band noise being aliased. Important to the specification of both the ADC and its clocking Phase- Locked Loop (PLL) is jitter. Contributing to the system jitter are the aperture jitter of the sample-and-hold switch at the input of ADC and the sampling-clock jitter. Aperture jitter effects have usually been modeled as additive noise, based on a sinusoidal input signal, and limits the achievable Signal-to-Noise Ratio (SNR). Jitter in the sampled signal has several sources: phase noise in the Voltage-Controlled Oscillator (VCO) within the sampling PLL, jitter introduced by variations in the period of the frequency divider used in the sampling PLL and cross-talk from the lock line running parallel to signal lines. Jitter in the sampling process directly acts to degrade the noise floor and selectivity of receiver. Choosing an appropriate VCO for a SWR system is not as simple as finding one with right oscillator frequency. Similarly, it is important to specify the right jitter performance for the ADC. In this paper, the allowable sampling frequencies are calculated and analyzed for the multiple frequency BPS software radio GNSS receivers. The SNR degradation due to jitter in a BPSK system is calculated and required jitter standard deviation allowable for each GNSS band of interest is evaluated. Furthermore, in this paper we have investigated the sources of jitter and a basic jitter budget is calculated that could assist in the design of multiple frequency SWR GNSS receivers. We examine different ADCs and PLLs available in the market and compare known performance with the calculated budget. The results obtained are therefore directly applicable to SWR GNSS receiver design.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.6
• /
• pp.1250-1259
• /
• 2012

In this paper, a time-domain comparator is proposed for a successive approximation (SA) analog-to-digital converter (ADC) with a low power and high resolution. The proposed time-domain comparator consists of a voltage-controlled delay converter with a clock feed-through compensation circuit, a time amplifier, and binary phase detector. It has a small input capacitance and compensates the clock feed-through noise. To analyze the performance of the proposed time-domain comparator, two 1V 10-bit 200-kS/s SA ADCs with a different time-domain comparator are implemented by using 0.18-${\mu}m$ 1-poly 6-metal CMOS process. The measured SNDR of the implemented SA ADC is 56.27 dB for the analog input signal of 11.1 kHz, and the clock feed-through compensation circuit and time amplifier of the proposed time-domain comparator enhance the SNDR of about 6 dB. The power consumption and area of the implemented SA ADC are 10.39 ${\mu}W$ and 0.126 mm2, respectively.

• Korean Journal of Optics and Photonics
• /
• v.21 no.3
• /
• pp.123-128
• /
• 2010

Sum frequency generation was utilized to obtain a yellow laser with the wavelength of 578.4 nm for a probe laser of an Yb lattice clock. The output of an Nd:YAG laser with wavelength of 1319 nm and that of an Yb-fiber laser with wavelength of 1030 nm were passed through a waveguided periodically-poled lithium niobate (WG-PPLN) for sum frequency generation. It is required that the probe laser has a linewidth of the order of 1 Hz to fully resolve the Yb lattice clock transition. Thus, the linewidth of the probe laser was reduced by stabilizing the frequency to a super-cavity. This was made of ULE with a low thermal expansion coefficient, and was mounted on an active vibration-isolation table at the optimal point for the reduced sensitivity to vibration. Also, this was installed in a vacuum chamber, and the temperature was stabilized to 1 mK level. This system was installed in an acoustic enclosure to block acoustic noise. The finesse of the super-cavity was measured to be 380 000 from the photon life time of the cavity.

• Journal of information and communication convergence engineering
• /
• v.10 no.1
• /
• pp.85-90
• /
• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.6A
• /
• pp.871-880
• /
• 1999

In this paper, a pseudo-noise(PN) tracking and demodulation circuits are analyzed and designed for a direct-sequence/spread-spectrum multiple access system under a mobile fading channel. We consider noncoherent delay locked loop(DLL) as a PN code tracking loop which has 1/8 PN chip resolution. The tracking performance of DLL is evaluated in terms of locking time from a loose state and tracking jitter. The received signal is demodulated to original data by despreading with PN code locked by DLL. Also the designed circuit supports sound service of 32Kbps and in-band signal with 4.096MHz chip clock. The circuits are implemented and verified with FPGA, which is shown completely data recovery under AWGN 7dB and will be available for IMT-2000.