• 대한전자공학회논문지
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• 제26권11호
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• pp.1880-1885
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• 1989

In this paper, a new approach for systolic array realizing the discrete cosine transform (DCT) based on discrete Fourier transform (DFT) of an input sequence is presented. The proposed array is based on a simple modified DFT(MDFT) version of the Goertzel algorithm combined with Kung's approach and is proved perfectly. This array requires N cells, one multiplier and takes N clock cycles to produce a complete N-point DCT and also is able to process a continuous stream of data sequences. We have analyzed the output signal-to-noise ratio(SNR) and designed the circuit level layout of one-PE chip. The array coefficients are static adn thus stored-product ROM's can be used in place of multipliers to limit cost as eliminate errors due to coefficients quantization.

• IEIE Transactions on Smart Processing and Computing
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• 제3권4호
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• pp.161-166
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• 2014

An accurate gain-of-two amplifier, which successfully reduces the capacitor mismatch error is proposed. This amplifier has similar circuit complexity and linearity improvement to the capacitor error-averaging technique, but operates with two clock phases just like the conventional pipeline stage. This makes it suitable for high-speed, high-resolution analog-to-digital converters (ADCs). Two ADC architectures employing the proposed accurate gain-of-two amplifier are also presented. The simulation results show that the proposed ADCs can achieve 15-bit linearity with 8-bit capacitor matching.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.113-116
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• 2002

This paper describes a design of 8192-Point pipelined FFT/IFFT processor (PFFTSk) core for DVB-T and DMT-based VBSL modems. A novel two-step convergent block floating -point (75_CBFP) scaling method is proposed to improve the signal- to-quantization-noise ratio (SeNR) of FFT/IFFT results. Our approach reduces about 80% of memory when compared with conventional CBFP methods. The PFFTSk core, which is designed in VHDL and synthesized using 0.25-${\mu}{\textrm}{m}$ CMOS library, has about 76,300 gates, 390k bits RAM, and Twiddle factor ROM of 39k bits. Simulation results show that it can safely operate up to 50-MHz clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-$mutextrm{s}$. The SQNR of about 60-dB is achieved.

• 한국통신학회논문지
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• 제15권6호
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• pp.475-484
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• 1990

Direct Sequence 스펙트럼 확산방식에서 전원동기를 이용한 전원선 통신장치의 구성을 제안한 것이다. 전원선은 주파수대역폭이 일반적으로 10KHz~450KHz로 제한되어 있고, 특히 동기회로가 복잡해져서 제작가격이 높아지며 또한 시스템 규모가 커지며 다중통신하기가 어렵다. 동기회로를 이루기 위해서 교류전원에 동기하는 전원동기 Clock 발생회로를 제안하고 어드레스 설정기를 두어서 다중통신을 가능하게 하였다.

• 한국분말재료학회지
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• 제19권4호
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• pp.297-303
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• 2012

In this study, voltammetry system for realizing high sensitivity nano-labeled sensor of detecting heavy metals was designed, and optimal system operating conditions were determined. High precision digital to analog converter (DAC) circuit was designed to control applied unit voltage at working electrode and analog to digital converter (ADC) circuit was designed to measure the current range of $0.1{\sim}1000{\mu}A$ at counter electrode. Main control unit (MCU) circuit for controlling voltammetry system with 150 MHz clock speed, main memory circuit for the mathematical operation processing of the measured current value and independent power circuit for analog/digital circuit parts to reduce various noise were designed. From result of voltammetry system operation, oxidation current peaks which are proportional to the concentrations of Zn, Cd and Pb ions were found at each oxidation potential with high precision.

• ETRI Journal
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• 제29권1호
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• pp.79-88
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• 2007

This paper proposes a novel concept of adjusting the hardware size in a multi-carrier code division multiple access (MC-CDMA) receiver in real time as per the channel parameters such as delay spread, signal-to-noise ratio, transmission rate, and Doppler frequency. The fast Fourier transform (FFT) or inverse FFT (IFFT) size in orthogonal frequency division multiplexing (OFDM)/MC-CDMA transceivers varies from 1024 points to 16 points. Two low-power reconfigurable radix-4 256-point FFT processor architectures are proposed that can also be dynamically configured as 64-point and 16-point as per the channel parameters to prove the concept. By tailoring the clock of the higher FFT stages for longer FFTs and switching to shorter FFTs from longer FFTs, significant power saving is achieved. In addition, two 256 sub-carrier MC-CDMA receiver architectures are proposed which can also be configured for 64 sub-carriers in real time to prove the feasibility of the concept over the whole receiver.

• 한국음향학회지
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• 제17권8호
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• pp.103-109
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• 1998

디지털신호의 변조에는 기본적으로 진폭 편이 변조(ASK: Amplitude-Shift Keying), 주파수 편이 변조(FSK: Frequency-Shift Keying), 위상 편이 변조(PSK: Phase-Shift Keying) 등의 세 가지 방법이 있다. 본 논문에서는 표본클록 합성계수 방식에 관한 이론을 고찰하고, 클록초기치 누적방식의 DDFS를 이용하여 위에서 언급한 변조방법을 실현할 수 있는 주파수 도약 대역 확산 통신에 적합한 변조기를 구현하였다. 또한, 합성된 출력주파수 의 정현파형에 대한 스펙트럼 분석과 PN(Pseudo Noise) 부호를 사용한 순시적인 주파수 도 약 상태, 위상제어의 가능성 등을 확인한 결과 실험으로부터 다음과 같은 결과를 얻었다. 첫 째, 합성된 출력주파수는 주파수 Index에 따라 기준주파수에 정확히 정수배가 되며, 둘째, 합성된 정현파형의 스펙트럼으로 기본파와 여러 고조파의 크기를 비교하여 본 결과 50[dB] 이상의 차이가 남으로서 고조파 성분들이 상당히 감소되었음을 확인하였고, 셋째, PN 코드 를 사용하여 순시적인 주파수 도약 상태를 확인하여 본 결과 스위칭 시간이 빠르기 때문에 주파수 도약 특성이 뛰어남을 알 수 있었으며 또한, 누산기의 set/reset 상태를 변화시킴에 따라 위상이 제어됨을 입증하였다.

• 한국전자파학회논문지
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• 제9권1호
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• pp.98-107
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• 1998

FM-DS /SS 시스댐 구현을 위하여, 주입되는 신호에 동기하는 주입형 SO (Synchronous Oscillator)에 대하 여 해석하였다. 송신부에서는 FM의 RF 출력 신호와 DS /SS(Direct Sequence /Spread Spectrum)을 이용하 여 FM-DS /SS 변조 방식을 채택하였으며, 수신부에서는,SO를 수신부의 PN(Pusudo Noise) 클럭 동기를 위한 슬라이딩 상관기로 사용하여 FM-DS/SS의 복조를 위한 동기부로 이용하였다. 그 결과 수신주파수가 도플러와 같은 현상에서도 안정된 동기성능을 유지하였으며, FM-DS /SS의 시스템에 적용하여 PN 동기 및 동기 특성 을 입증하였다.

• 센서학회지
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• 제19권6호
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• pp.469-474
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• 2010

This paper presents a 10Gbps CMOS parallel-to-serial converter for transmission of sensor data. A low-noise clock multiplying unit(CMU) and a multiplexer with controllable data sequence are proposed. The transmitter was fabricated in 0.13 um CMOS process and the measured total output jitter was less than 0.1 UIpp(unit-interval, peak-to-peak) over 20 kHz to 80 MHz bandwidth. The jitter of the CMU output only was measured as 0.2 ps,rms. The transmitter dissipates less than 200 mW from 1.5 V/2.5 V power supplies.

• 센서학회지
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• 제29권3호
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• pp.149-155
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• 2020

In this study, we employed Manchester code for illumination control and flicker prevention of the light-emitting diode (LED) used in a visible light communication (VLC) system. In the VLC transmitter, the duty factor of the Manchester code was utilized for illumination control; in the VLC receiver, the spike signal from an RC-high pass filter was utilized to recover the transmitted signal whilst suppressing the 120-Hz noise arising from adjacent lighting lamps. Instead of the clock being transmitted in a separate channel, a syncmark signal was transmitted in front of each data byte and used as the reference time for transforming the Manchester code to non-return-to-zero (NRZ) data in the receiver. In experiments, the LED illumination was controlled in the range of approximately 12-84% of the constant wave (CW) light via changing of the duty factor from 10% to 90%. This scheme is useful for constructing indoor wireless sensor networks using LED light that is flicker-free and presents capability for illumination control.