• Journal of the Chungcheong Mathematical Society
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• v.23 no.4
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• pp.699-704
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• 2010

In this paper, we prove that the Hilbert 2-class field tower of an imaginary quadratic function field $F=k({\sqrt{D})$ is infinite if $r_2({\mathcal{C}}(F))=4$ and exactly one monic irreducible divisor of D is of odd degree, except for one type of $R{\acute{e}}dei$ matrix of F. We also compute the density of such imaginary quadratic function fields F.

• Communications of the Korean Mathematical Society
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• v.38 no.3
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• pp.715-723
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• 2023

In this paper, we construct explicitly an infinite family of primes P with h^±_P ≡ 0 (mod q^{deg P}), where h^±_P are the plus and minus parts of the divisor class number of the P-th cyclotomic function field over 𝔽_q(T). By using this result and Dirichlet's theorem, we give a condition of A, M ∈ 𝔽_q[T] such that there are infinitely many primes P satisfying with h^±_P ≡ 0 (mod p^e) and P ≡ A (mod M).

• Food Science of Animal Resources
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• v.43 no.4
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• pp.625-638
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• 2023

Among various biological agents, bacteriocins are important candidates to control Listeria monocytogenes which is a foodborne pathogen. In this study, a novel bacteriocin, named agilicin C7, was isolated from Ligilactobacillus agilis C7 showing inhibitory activity against L. monocytogenes. Agilicin C7 biosynthesis gene was characterized by bioinformatics analyses and heterologously expressed in Escherichia coli for further study. The anti-listeria activity of recombinant agilicin C7 (r-agilicin C7) was lost by proteases and α-amylase, suggesting that agilicin C7 is a glycoprotein. r-Agilicin C7 has wide pH and thermal stability and is also stable in various organic solvents. It destroyed L. monocytogenes by damaging the integrity of the cell envelope. These properties of r-agilicin C7 indicate that agilicin C7 is a novel amylase-sensitive anti-listerial Class IId bacteriocin. Physicochemical stability and inhibitory activity against L. monocytogenes of r-agilicin C7 suggest that it can be applied to control L. monocytogenes in the food industry, including dairy and meat products.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.7
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• pp.299-303
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• 2005

This paper proposes an analytic method can estimate delay time considering crosstalk noise at an arbitrary node of RC-class interconnects under saturated ramp input using a simple closed-form expression. In the case of single interconnects, algebraic expression presented in existent research can estimate delay time under ramp input using delay time under step input, and we applied it to estimate delay time considering crosstalk noise. As the result, we can provide a intuitive analysis about signal integrity of circuits that include crosstalk noise reducing computational complexity significantly.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.19-26
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• 1997

Novel class AB CMOS second-generation current conveyors (CCII) using 0.6.mu.m n-well CMOS process for high-frequency current-mode signal processing were developed. The CCII for low power operation consists of a class AB push-pull stage for the current input, a complementary source follower for the voltage input, and a cascode current mirror for the current output. In this architecture, the two input stages are coupled by current mirrors to reduce the current input impedance. Measurements of the fabricated CCII show that the current input impedance is 875.ohm. and the bandwidth of flat gain when used as a voltage amplifier extends beyond 4MHz. The power dissipation is 1.25mW and the active chip area is 0.2*0.15[mm$\^$2/].

• Journal of Advanced Marine Engineering and Technology
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• v.29 no.6
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• pp.618-627
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• 2005

In this paper, we have compared and analyzed the performance of high amplifier using Doherty technique to improve linearity and efficiency of base station and repeater Power amplifier for WCDMA. This Doherty amplifier implements with 3dB branch line coupler and $90^{\circ}C$ transmission line The phase offset line is designed to maintain the high linearity and efficiency at the low efficiency Period of the power amplifier CW 1-tone experimental results at the WCDMA frequency $2.11{\sim}2.17GHz$ shows that Doherty amplifier which achieves power add efficiency(PAE) of 50% at 6dB back off the point from maximum output power 52.3 dBm, obtains higher efficiency of 13.3% than class AB Finding optimum bias Point after adjusted gate voltage, Doherty amplifier shows that $IMD_3$ improves 4dB.

• 한국초전도학회:학술대회논문집
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• v.10
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• pp.226-229
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• 2000

Long lengths (<100m) of BSCCO 2223 tapes were fabricated of optimal process. We have I$_c$${\sim}$22A, J$_c$${\sim}$22,000A/cm$^2$(77K, 0T) at last heat treatment, and then prototype 1000A class current lead (length ${\sim}$50cm) fur HTS applications was fabricated using these tapes. Surface of current lead except both end part (${\sim}$1cm) was clothing with fiber glass. Also the transportation properties and thermal loss was studied on prototype 1000A class current lead.

• Journal of Institute of Control, Robotics and Systems
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• v.13 no.1
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• pp.46-51
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• 2007

In this paper, we propose a new data clustering method using local probability and hypothesis theory. To cluster the test data set we analyze the local area of the test data set using local probability distribution and decide the candidate class of the data set using mean standard deviation and variance etc. To decide each class of the test data, statistical hypothesis theory is applied to the decided candidate class of the test data set. For evaluating, the proposed classification method is compared to the conventional fuzzy c-mean method, k-means algorithm and Discriminator analysis algorithm. The simulation results show more accuracy than results of fuzzy c-mean method, k-means algorithm and Discriminator analysis algorithm.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.4
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• pp.200-207
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• 2004

This paper presents a simple and fast delay metric RC-class interconnects under saturated ramp inputs. The RC delay metric under saturated ramp inputs, called FDM(Fast Delay Metric), can estimate delay times at an arbitrary node using a simple closed-form expression and is extended from delay metric under step input easily As compared with similar techniques proposed in previous researches, it is shown that the FDM technique complexity for a similar accuracy. As the number of circuit nodes increases, there will be a significant difference in estimation times of RC delay between the previous techniques based on two circuit moments and the FDM which do not depend on circuit moments.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.5
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• pp.193-200
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• 2003

This Paper analyses several model-order reduction methods and then proposes an improved n model and a new delay calculation method to be used in analyzing RC-class interconnects, which does not involve moment calculation processes. The proposed delay calculation method has been derived by combining the unproved $\pi$ model, the concept of effective capacitance and Elmore delay. This method has an advantage in that it can be applied in the calculation of end-to-end delay as well as incremental delay.