• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.1
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• pp.68-75
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• 2011

The performance of peripheral devices is improving rapidly to meet the needs of users for multimedia data. Therefore, the peripheral interface with wide bandwidth and high transmission rate becomes necessary to handle large amounts of data in real time for multiple high-performance devices. PCI Express is a fast serial interface with the use of packets that are compatible with previous PCI and PCI-X. In this paper, we design and verify general peripheral interface using serial link. It includes two kinds of traffic class (TC) labels which are mapped to virtual channels (VC). The design adopts TC/VC mapping and the scheme of arbitration by priority. The design uses a packet which can be transmitted through up to four transmission lanes. The design of general peripheral interface is described in Verilog HDL and verified using ModelSim. For FPGA verification, Xilinx ISE and SPARTAN XC3S400 are used.We used Synopsys Design Compiler as a synthesis tool and the used library was MagnaChip 0.35um technology.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.3
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• pp.255-263
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• 2000

A multistage interconnection network is a suitable class of interconnection architecture for constructing large-scale multicomputers. Broadcast and multicast communication are fundamental in supporting collective communication operations such as reduction and barrier synchronization. In this paper, we propose a new multicast technique in wormhole-switched bidirectional multistage banyan networks for constructing large-scale multicomputers. To efficiently support broadcast and multicast with simple additional hardware without deadlock, we propose a two-phase multicast algorithm which takes only two transmissions to perform a broadcast and a multicast to an arbitrary number of desired destinations. We encode a header as a cube and adopt the most upper input link first scheme with periodic priority rotation as arbitration mechanism on contented output links. We coalesce the desired destination addresses into multiple number of cubes. And then, we evaluate the performance of the proposed algorithm by simulation. The proposed two-phase multicast algorithm makes a significant improvement in terms of latency. It is noticeable that the two-phase algorithm keeps broadcast latency as efficient as the multicast latency of fanout 2^m where m is the minimum integer satisfying $2^m{\geq} {\sqrt{N}}$ ( N is a network size).