• 제목/요약/키워드: Circuit integration

검색결과 293건 처리시간 0.028초

네오프렌(Neoprene)소재로 구성된 골프자세 훈련용 웨어러블 디바이스의 실용적 기능에 관한 연구: Flex Sensor 및 아두이노를 장착한 보조밴드를 중심으로 (A Study on Practical Function of Neoprene Fabric Design in wearable Device for Golf Posture Training: Focus on Assistance Band with Arduino/Flex Sensor)

  • 이은아;김종준
    • 패션비즈니스
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    • 제18권4호
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    • pp.1-14
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    • 2014
  • Currently smart textile market is rapidly expanding and the demand is increasing integration of an electronic fiber circuit. The garments are an attractive platform for wearable device. This is one of the integration techniques, which consists of is the selective introduction of conductive yarns into the fabric through knitting, weaving or embroidering. The aim of this work is to develop a golf bend driven prototype design for an attachable Arduino that can be used to assess elbow motion. The process begins with the development of a wearable device technique that uses conductive yarn and flex sensor for measurement of elbow bending movements. Also this paper describes and discusses resistance value of zigzag embroidery of the conductive yarns on the tensile properties of the fabrics. Furthermore, by forming a circuit using an Arduino and flex sensor the prototype was created with an assistance band for golf posture training. This study provides valuable information to those interested in the future directions of the smart fashion industry.

전극형성과 태양전지 모듈 일체화 기술 개발에 적용되는 태양전지 전극 설계 기술 (Electrode Design for Electrode Formation and PV Module Integration Development)

  • 박진주;전영우;장민규;김민제;임동건
    • Current Photovoltaic Research
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    • 제9권4호
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    • pp.123-127
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    • 2021
  • This study was on electrode design for the realization of a solar cell that combines electrode formation and module integration process to overcome printing limitations. We used the passivated emitter rear contact (PERC) solar cell. Wafer size was 156.75 mm ×156.75 mm. The fabricated cell results showed that the open-circuit voltage of 649 mV, short-circuit current density of 36.15 mA/cm2, fill factor of 68.5%, and efficiency of 16.06% with electrode conditions the 24BBs with the width 190 ㎛ and 90FBs with the width 45 ㎛. For improving efficiency, the characteristics of the solar cell were checked according to the change in the number of BBs and FBs and the change in line fine width. It is confirmed that the efficiency of the solar cell will be improved by increasing the number of FBs from 90 to 120, and increasing the line width of the FBs by about 10 ㎛ compared to the manufacturing solar cells.

BMS용 능동밸런싱 회로 소자 구동용 게이트 구동 칩 설계 (Design of a gate driver driving active balancing circuit for BMSs.)

  • 김영희;김홍주;하윤규;하판봉;백주원
    • 한국정보전자통신기술학회논문지
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    • 제11권6호
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    • pp.732-741
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    • 2018
  • 여러 배터리 셀을 직렬로 연결해서 사용하는 BMS에서 사용 가능 용량을 최대화시키기 위하여 각 셀의 전압을 같도록 맞춰주는 셀 밸런싱 기술이 필요하다. 다중 권선 변압기를 사용하는 능동 셀 밸런싱 회로에서 셀 간 직접적 (direct cell-to-cell)으로 에너지를 전달하는 밸런싱 회로는 PMOS 스위치와 NMOS 스위치를 구동하기 위한 게이트 구동 칩은 PMOS 스위치와 NMOS 스위치 개수 만큼 TLP2748 포토커플러(photocoupler)와 TLP2745 포토커플러가 필요하므로 원가가 증가하고 집적도가 떨어진다. 그래서 본 논문에서는 포토커플러를 사용하여 PMOS와 NMOS 스위칭소자를 구동하는 대신 70V BCD 공정기반의 PMOS 게이트 구동회로와 NMOS 게이트 구동회로, 스위칭 시간이 개선된 PMOS 게이트 구동회로와 NMOS 게이트 구동회로를 제안하였다. 스위칭 시간이 개선된 PMOS 게이트 구동 스위치의 ${\Delta}t$는 8.9ns이고, NMOS 게이트 구동 스위치의 ${\Delta}t$는 9.9ns로 양호한 결과를 얻었다.

Novel Bumping and Underfill Technologies for 3D IC Integration

  • Sung, Ki-Jun;Choi, Kwang-Seong;Bae, Hyun-Cheol;Kwon, Yong-Hwan;Eom, Yong-Sung
    • ETRI Journal
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    • 제34권5호
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    • pp.706-712
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    • 2012
  • In previous work, novel maskless bumping and no-flow underfill technologies for three-dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low-volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no-flow underfill material named "fluxing underfill" is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two-tier stacked TSV chips are sucessfully stacked.

Investigating the Effects of Hearing Loss and Hearing Aid Digital Delay on Sound-Induced Flash Illusion

  • Moradi, Vahid;Kheirkhah, Kiana;Farahani, Saeid;Kavianpour, Iman
    • 대한청각학회지
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    • 제24권4호
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    • pp.174-179
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    • 2020
  • Background and Objectives: The integration of auditory-visual speech information improves speech perception; however, if the auditory system input is disrupted due to hearing loss, auditory and visual inputs cannot be fully integrated. Additionally, temporal coincidence of auditory and visual input is a significantly important factor in integrating the input of these two senses. Time delayed acoustic pathway caused by the signal passing through digital signal processing. Therefore, this study aimed to investigate the effects of hearing loss and hearing aid digital delay circuit on sound-induced flash illusion. Subjects and Methods: A total of 13 adults with normal hearing, 13 with mild to moderate hearing loss, and 13 with moderate to severe hearing loss were enrolled in this study. Subsequently, the sound-induced flash illusion test was conducted, and the results were analyzed. Results: The results showed that hearing aid digital delay and hearing loss had no detrimental effect on sound-induced flash illusion. Conclusions: Transmission velocity and neural transduction rate of the auditory inputs decreased in patients with hearing loss. Hence, the integrating auditory and visual sensory cannot be combined completely. Although the transmission rate of the auditory sense input was approximately normal when the hearing aid was prescribed. Thus, it can be concluded that the processing delay in the hearing aid circuit is insufficient to disrupt the integration of auditory and visual information.

다중(multiple) TSV-to-TSV의 임피던스 해석 (The Impedance Analysis of Multiple TSV-to-TSV)

  • 이시현
    • 전자공학회논문지
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    • 제53권7호
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    • pp.131-137
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    • 2016
  • 본 논문에서는 기존의 2D IC의 성능을 개선하고 3D IC의 집적도와 전기적인 특성을 개선하기 위한 목적으로 연구되고 있는 TSV (Through Silicon Via)의 임피던스를 해석하였다. 향후 Full-chip 3D IC 시스템 설계에서 TSV는 매우 중요한 기술이며, 높은 집적도와 광대역폭 시스템 설계를 위해서 TSV에 대한 전기적인 특성에 관한 연구가 매우 중요하다. 따라서 본 연구에서는 Full-chip 3D IC를 설계하기 위한 목적으로 다중 TSV-to-TSV에서 거리와 주파수에 따른 TSV의 임피던스 영향을 해석하였다. 또한 이 연구 결과는 Full-chip 3D IC를 제조하기 위한 반도체 공정과 설계 툴에 적용할 수 있다.

Wind Power Grid Integration of an IPMSG using a Diode Rectifier and a Simple MPPT Control for Grid-Side Inverters

  • Ahmed, Tarek;Nishida, Katsumi;Nakaoka, Mutsuo
    • Journal of Power Electronics
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    • 제10권5호
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    • pp.548-554
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    • 2010
  • In this paper, a 1.5 kW Interior Permanent Magnet Synchronous Generator (IPMSG) with a power conditioner for the grid integration of a variable-speed wind turbine is developed. The power-conditioning system consists of a series-type 12-pulse diode rectifier powered by a phase shifting transformer and then cascaded to a PWM voltage source inverter. The PWM inverter is utilized to supply sinusoidal currents to the utility line by controlling the active and reactive current components in the q-d rotating reference frame. While the q-axis active current of the PWM inverter is regulated to follow an optimized active current reference so as to track the maximum power of the wind turbine. The d-axis reactive current can be adjusted to control the reactive power and voltage. In order to track the maximum power of the wind turbine, the optimal active current reference is determined by using a simple MPPT algorithm which requires only three sensors. Moreover, the phase angle of the utility voltage is detected using a simple electronic circuit consisting of both a zero-crossing voltage detecting circuit and a counter circuit employed with a crystal oscillator. At the generator terminals, a passive filter is designed not only to decrease the harmonic voltages and currents observed at the terminals of the IPMSG but also to improve the generator efficiency. The laboratory results indicate that the losses in the IPMSG can be effectively reduced by setting a passive filter at the generator terminals.

램프-적분을 이용한 용량치-시간차 변환기 및 디지털 습도 조절기에의 응용 (A Capacitance Deviation-to-Time Interval Converter Based on Ramp-Integration and Its Application to a Digital Humidity Controller)

  • 박지만;정원섭
    • 대한전자공학회논문지SD
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    • 제37권12호
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    • pp.70-78
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    • 2000
  • 새로운 램프-적분을 이용한 용량차-시간차 변환기를 제안했다. 제안된 회로는 상하대칭으로 두개의 전류 미러, 두 개의 슈미트 트리거, 그리고 제어 논리-회로로 구성된다. 전체 회로를 개별 소자들로 꾸며, 실험한 결과, 제안된 변환기의 센서 커패시터가 295㎊에서 375㎊까지의 커패시턴스 변화에서 1%보다 작은 시간간격(펄스 폭)의 선형 오차를 가진다는 것을 알았다. 제안된 변환기가 335㎊의 센서 커패시턴스를 가질 때, 측정된 용량차와 시간차는 각각 40㎊와 0.2ms이었다. 이 시간차를 빠르고 안정된 클럭으로 카운트함으로써 고 분해능을 제공한다는 것을 알았다. 새로운 램프-적분을 이용한 용량차-시간차변환기를 사용하여 디지털 습도 조절기를 설계하고 실험하였다. 제안된 회로는 전원 전압이나 온도 변화에도 불구하고 용량차에는 거의 영향을 받지 않는다. 또한, 제한된 회로는 적은 수의 MOS 소자로 실현되므로, 작은 칩 면적 위에 집적화 할 수 있는 특징을 갖는다. 따라서 이 회로는 온-칩(on-chip) 인터페이스 회로로 적합하다.

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Sn-3.0Ag-0.5Cu 솔더링에서 플럭스 잔사가 전기화학적 마이그레이션에 미치는 영향 (Flux residue effect on the electrochemical migration of Sn-3.0Ag-0.5Cu)

  • 방정환;이창우
    • Journal of Welding and Joining
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    • 제29권5호
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    • pp.95-98
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    • 2011
  • Recently, there is a growing tendency that fine-pitch electronic devices are increased due to higher density and very large scale integration. Finer pitch printed circuit board(PCB) is to be decrease insulation resistance between circuit patterns and electrical components, which will induce to electrical short in electronic circuit by electrochemical migration when it exposes to long term in high temperature and high humidity. In this research, the effect of soldering flux acting as an electrical carrier between conductors on electrochemical migration was investigated. The PCB pad was coated with OSP finish. Sn3.0Ag0.5Cu solder paste was printed on the PCB circuit and then the coupon was treated by reflow process. Thereby, specimen for ion migration test was fabricated. Electrochemical migration test was conducted under the condition of DC 48 V, $85^{\circ}C$, and 85 % relative humidity. Their life time could be increased about 22% by means of removal of flux. The fundamentals and mechanism of electrochemical migration was discussed depending on the existence of flux residues after reflow process.

피드백 전계 효과 트랜지스터의 메크로 모델링 연구 (Macro Modeling of a Feedback Field-effect Transistor)

  • 오종혁;유윤섭
    • 한국정보통신학회:학술대회논문집
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    • 한국정보통신학회 2021년도 추계학술대회
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    • pp.634-636
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    • 2021
  • 이번 연구에서는 피드백 전계 효과 트랜지스터(feedback field-effect transistor, FBFET)의 메크로 모델링에 대한 연구를 SPICE 시뮬레이터를 통해 진행했다. 기존에 제시된 FBFET의 메크로 모델은 두 개의 회로로 구성돼 있으며, 하나는 전하 축적 기능을 구현한 회로이며 다른 하나는 전류 생성 회로이다. 기존 전류 생성회로는 IDS-VGS 특성만 구현 가능하여 회로 예측에 어려움이 있다. 이를 해결하기 위해 전류 생성 회로에 다이오드를 추가함으로 IDS-VDS 특성까지 구현 가능한 모델을 제시한다.

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