• Journal of IKEEE
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• v.23 no.3
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• pp.1061-1067
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• 2019

In this paper, a highly integrated 3-channel DC-DC converter is designed using power transistor width scaling (PTWS). For positive voltage, $V_{POS}$, a boost converter is designed using the set-time variable pulse width modultaion (SPWM) dual-mode and PTWS to improve efficiency at light load. For negative voltage, $V_{NEG}$, a 0.5 x regulated inverting charge pump is designed with pulse skipping modulation (PSM) controller to reduce power consumption, and for an additional positive voltage, $V_{AVDD}$, a LDO circuit is designed. The proposed DC-DC converter has been designed using a $0.18{\mu}m$ BCDMOS process. Simulation results show that the proposed converter has power efficiency of 56%~90% for load current range of 1 mA~70 mA and output ripple voltage less than 5 mV at positive voltage.

• Korean Journal of Optics and Photonics
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• v.30 no.4
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• pp.146-153
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• 2019

The exposure system is a device that transfers a circuit pattern to a desired location. To display patterns on a substrate without deforming the optical characteristics, the characteristics of the optical exposure system are very important. Therefore, to form a microcircuit pattern, a small divergence angle should impinge on the irradiation area. Also, since the light from the source must react uniformly with the photosensitizer, it must have high luminance efficiency and uniformity of illumination. In this paper a parabolic reflector and an aspherical lens were designed to solve the problem of narrow-angle implementation, and it was confirmed by simulation analysis after their arrangement that the beam angle, uniformity, and maximum illuminance satisfied the target performance.

• Journal of IKEEE
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• v.23 no.1
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• pp.58-67
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• 2019

A design of an elliptic curve cryptography (ECC) processor that supports both pseudo-random curves and Koblitz curves over $GF(2^m)$ defined by the NIST standard is described in this paper. A finite field arithmetic circuit based on a word-based Montgomery multiplier was designed to support five key lengths using a datapath of fixed size, as well as to achieve a lightweight hardware implementation. In addition, Lopez-Dahab's coordinate system was adopted to remove the finite field division operation. The ECC processor was implemented in the FPGA verification platform and the hardware operation was verified by Elliptic Curve Diffie-Hellman (ECDH) key exchange protocol operation. The ECC processor that was synthesized with a 180-nm CMOS cell library occupied 10,674 gate equivalents (GEs) and a dual-port RAM of 9 kbits, and the maximum clock frequency was estimated at 154 MHz. The scalar multiplication operation over the 223-bit pseudo-random elliptic curve takes 1,112,221 clock cycles and has a throughput of 32.3 kbps.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.4
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• pp.643-652
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• 2021

Accidents or faults in the transmission and distribution system are never completely avoidable, and short-circuit and earth faults are occurs despite the efforts of the TSO and DSO. Recently, the connection to the transmission and distribution system of large-capacity new and renewable distributed power has increased rapidly and has various effects on the operation of the system. In order to minimize this, connection standards such as FRT (Fault-Ride-Through) have been established to provide wind turbines or solar inverters. In the event of a major faults of the power system, the operation support shall be provided so that the operator can stably operate the system by smoothly performing connection maintenance or rapid system separation. In this paper, in order to appropriately determine whether the FRT condition, which is the grid connection criterion for a representative DERs, is sufficient, a detection system using a PMU (Phasor Measurement Unit) that measures a synchro-phasors was designed and deployment and a system accident due to a generator step-out to analyze and evaluate the proposed system based on the case.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.2
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• pp.268-275
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• 2020

A lightweight hardware design of self-timed ring based true random number generator (TRNG) suitable for information security applications is described. To reduce hardware complexity of TRNG, an entropy extractor with feedback structure was proposed, which minimizes the number of ring stages. The number of ring stages of the FSTR-TRNG was determined to be a multiple of eleven, taking into account operating clock frequency and entropy extraction circuit, and the ratio of tokens to bubbles was determined to operate in evenly-spaced mode. The hardware operation of FSTR-TRNG was verified by FPGA implementation. A set of statistical randomness tests defined by NIST 800-22 were performed by extracting 20 million bits of binary sequences generated by FSTR-TRNG, and all of the fifteen test items were found to meet the criteria. The FSTR-TRNG occupied 46 slices of Spartan-6 FPGA device, and it was implemented with about 2,500 gate equivalents (GEs) when synthesized in 180 nm CMOS standard cell library.

• Journal of IKEEE
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• v.24 no.4
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• pp.1093-1097
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• 2020

This work describes the design and characterization of a Ku-band monolithic microwave integrated circuit (MMIC) power amplifier (PA) for satellite communication applications. The device technology used relies on 0.25 ㎛ gate length gallium arsenide (GaAs) pseudomorphic high electron mobility transistor (PHEMT) of wireless information networking (WIN) semiconductor foundry. The developed Ku-band PHEMT MMIC power amplifier has a small-signal gain of 22.2~23.1 dB and saturated output power of 34.8~35.4 dBm over the entire band of 13.75 to 14.5 GHz. Maximum saturated output power is a 35.4 dBm (3.47 W) at 13.75 GHz. Its power added efficiency (PAE) is 30.6~37.83% and the chip dimensions are 4.4 mm×1.9 mm. The developed 3 W PHEMT MMIC power amplifier is expected to be applied in a variety of Ku-band satellite communication applications.

• Journal of the Korean Society of Industry Convergence
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• v.23 no.6_2
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• pp.971-977
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• 2020

In this paper, We propose a portable electrostatic meter which can measure high voltage static electricity caused by friction to prevent fire or explosion accidents in grinding, crushing, power injection, transport, filling, dust removal, painting, and foreign matter removal processes. The proposed device not only shows static electricity strength in 4 steps with respect to distance and voltage but also gives warning with a buzzer, on process facilities that are likely to generate high voltage static electricity due to friction. The device is implemented by filtering the signal detected by the wireless antenna, amplifying the signal by 6 times, and passing the signal through the integrator circuit. Tests are carried out with an electrostatic discharge simulator. And the results show that 4 LEDs are turned on at the distance of 10cm, 3 LEDs at 12cm, 2 LEDs at 13cm, and 1 LED at 15cm, when a fixed voltage of 500V is given. And also, the tests show that the static electricity can be detected at 5cm on 100V, 10cm on 200V, 15cm on 500V, 20cm on 1000V, and 25cm on 1500V. We expect to reduce accidents caused by static electricity by allowing safety managers on fields where fire or explosion accidents can happen to monitor static electricity.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.3
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• pp.137-142
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• 2021

In recent years, permanent magnets such as IPM (Interior Permanent Magnet) motors or SPM (Surface Permanent Magnet) motors that can obtain high efficiency and power density by inserting rare earth permanent magnets into the rotor are used. Research on the used electric motor is being actively conducted. Since it uses a permanent magnet, it has the advantage of high efficiency and high power density compared to reluctance motors and induction motors, but by inserting a permanent magnet into the rotor, it operates at high speeds and decreases reliability due to demagnetization of the permanent magnets, and increases the cost of rare earth metals. In this paper, in accordance with the development of future technology that can replace rare-earth permanent magnet motors and technological preoccupation of rare-earth reduction type motors and de-rare-earth motors, switched reluctance motors that do not require permanent magnets (Switched Reluvtance Motors) Motor, SRM) to drive driving control. Using the 3-phase SRM library provided by the PSIM simulation program, we will study the driving and control system modeling of SRM using the rotor position information sensor.

• Journal of Digital Convergence
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• v.19 no.6
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• pp.233-238
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• 2021

Recently, blockchain technology accumulates and stores all transactions. Therefore, in order to verify the contents of all transactions, the data itself is compressed, but the scalability is limited. In addition, since a separate verification algorithm is used for each type of transaction, the verification burden increases as the size of the transaction increases. Existing blockchain cannot participate in the network because it does not become a block sink by using a server with a low specification. Due to this problem, as the time passes, the data size of the blockchain network becomes larger and it becomes impossible to participate in the network except for users with abundant resources. Therefore, in this paper, we are improved transaction as studied the zero knowledge proof algorithm for general operation verification. In this system, the design of zero-knowledge circuit generator capable of general operation verification and optimization of verifier and prover were also conducted.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.12
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• pp.1609-1617
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• 2019

Described in this paper is a design of hardware accelerator for implementing public-key cryptographic protocols (PKCPs) based on Elliptic Curve Cryptography (ECC) and RSA. It supports five elliptic curves (ECs) over GF(p) and three key lengths of RSA that are defined by NIST standard. It was designed to support four point operations over ECs and six modular arithmetic operations, making it suitable for hardware implementation of ECC- and RSA-based PKCPs. In order to achieve small-area implementation, a finite field arithmetic circuit was designed with 32-bit data-path, and it adopted word-based Montgomery multiplication algorithm, the Jacobian coordinate system for EC point operations, and the Fermat's little theorem for modular multiplicative inverse. The hardware operation was verified with FPGA device by implementing EC-DH key exchange protocol and RSA operations. It occupied 20,800 gate equivalents and 28 kbits of RAM at 50 MHz clock frequency with 180-nm CMOS cell library, and 1,503 slices and 2 BRAMs in Virtex-5 FPGA device.