• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.11 no.4
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• pp.63-69
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• 2012

This paper describes novel scheme of a gray scale capacitive fingerprint image for high-accuracy capacitive sensor chip. The typical gray scale image scheme used a DAC of big size layout or charge-pump circuit of non-volatile memory with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit of charge sharing scheme is proposed, which uses DLC(down literal circuit) based on a neuron MOS(vMOS) and analog simple multiplexor. The detection circuit is designed and simulated in 3.3V, $0.35{\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, a pixel layout size can be reduced and the image resolution can be improved.

• Journal of Korea Society of Digital Industry and Information Management
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• v.18 no.1
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• pp.1-9
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• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.1
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• pp.38-46
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• 1992

In this thesis, a high speed code synchronization circuit is implemented, which is applicable to frequency hopping FSK tranceiver within 68-88 MIBz band- width. synchronization Process consists of two steps, initial synchronization and tracking. A modified matched filter method using two channel passive correlators matched with short hopping frequencies, synchronization prcfix. is proposed for initial synchronization. To increase probability of initial synchronization, prefix are transmitted repeatedly. The outputs of correlators are sent to synchronization decision circuit, and code start time Is extracted by synchronizatlon decision circuit-Modified matched fitter method makes it possible to reduce complexity in hardware and obtain code acquisition rapidly.Clock recovery circuit regenerates PN code clock for tracking.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.11
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• pp.56-64
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• 1992

The sum-of-product type MVL (Multiple-valued logic) functions can be directly transformed into the exclusive-sum-of-literal-product(ESOLP) type MVL functions with a substitution of the OR operator with the exclusive-OR(XOR) operator. This paper presents an algorithm that can reduce the number of minterms for the purpose of minimizing the hardware size and the complexity of the circuit in the realization of ESOLP-type MVL functions. In Boolean algebra, the joinable true minterms can form the cube, and if some cubes form a cube-chain with adjacent cubes by the insertion of false cubes(or, false minterms), then the created cube-chain can become a large cube which includes previous cubes. As a result of the cube grouping, the number of minterms can be reduced artificially. Since ESOLP-type MVL functions take the MIN/XOR structure, a XOR circuit and a four-valued MIN/XOR dynamic-CMOS PLA circuit is designed for the realization of the minimized functions, and PSPICE simulation results have been also presented for the validation of the proposed algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.6
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• pp.1175-1183
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• 2001

In this paper, we use hyper chaos circuit which is made through the phase differences which is generated during the process of weak-coupling of CNN between two and more chaos attractors. Notwithstanding the complexity of the hyper chaos, we could do the synchronization and according to it, Secure communication through this method coo]d be accomplished. On this research, we configurated 2-double scroll and 3-double scroll circuit ,not using Chua circuit, but SC-CNN(State-Controlled CNN) which is more flexible to configure the system.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.4
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• pp.174-179
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• 2002

In this paper, the modified simulation algorithms of the Auto Transformer (AT) feeding electric train system were proposed. To obtain terminal voltage of train by using equivalent circuit or the AT feeding system, the iterative method is proposed for which determine the train voltages. The train voltages are iteratively calculated from the system voltage drop and line impedance. In the carte study, the proposed method is verified from actual operation data of the Kwa-Chon line. Also it is verified that the proposed method can be extent to the multi-train simulation tool. The terminal voltage of the multi-train can be calculated by using superposition principle and it is easily applied to the proposed method. Therefore, the proposed method can be a solution for the complexity of the circuit analysis in the existing methods.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.55-57
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• 1997

This paper develops the advanced method for the calculation of the equivalent circuit parameters of induction motor. An Induction motor is magnetically coupled system. But the conventional motor (the permeance method) calculates the each component of parameters separately. And it highly depends on the experimental factors and experiences to compensate the errors due to the some assumptions. Rut the proposed method calculates the parameters fully from the results of 2 dimensional finite element analysis. So the complexity in geometry and the non linearity of induction motor can be considered. And the computational cost is reduced compared with the conventional field and circuit approach. The results are compared with parameters from the permeance method. And it is verified by the comparison with the experimental results.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.4
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• pp.200-207
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• 2004

This paper presents a simple and fast delay metric RC-class interconnects under saturated ramp inputs. The RC delay metric under saturated ramp inputs, called FDM(Fast Delay Metric), can estimate delay times at an arbitrary node using a simple closed-form expression and is extended from delay metric under step input easily As compared with similar techniques proposed in previous researches, it is shown that the FDM technique complexity for a similar accuracy. As the number of circuit nodes increases, there will be a significant difference in estimation times of RC delay between the previous techniques based on two circuit moments and the FDM which do not depend on circuit moments.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.1
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• pp.45-50
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• 2001

With increasing complexity of digital logic circuits, fast and accurate verification of functional behaviour becomes most critical bottleneck in meeting time-to-market requirement. This paper presents several techniques for accelerating a cycle-based logic simulation. The acceleration techniques include parallel pattern logic evaluation, circuit size reduction, and the partition of feedback loops in sequential circuits. Among all, the circuit size reduction plays a critical role in maximizing logic simulation speedup by reducing 50% of entire circuit nodes on the average. These techniques are incorporated into a levelized table-driven logic simulation system rather than a compiled-code simulation algorithm. Finally, experimental results are given to demonstrate the effectiveness of the proposed acceleration techniques. Experimental results show more than 27 times performance improvement over single pattern levelized logic simulation.

• ETRI Journal
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• v.43 no.4
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• pp.728-745
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• 2021

Carbon nanotube field-effect transistors (CNTFETs) have been widely studied as a promising technology to be included in post-complementary metal-oxide-semiconductor integrated circuits. Despite significant advantages in terms of delay and power dissipation, the fabrication process for CNTFETs is plagued by fault occurrences. Therefore, developing a fast and accurate method for estimating the reliability of CNTFET-based digital circuits was the main goal of this study. In the proposed method, effects related to faults that occur in a gate's transistors are first represented as a probability transfer matrix. Next, the target circuit's graph is traversed in topological order and the reliabilities of the circuit's gates are computed. The accuracy of this method (less than 3% reliability estimation error) was verified through various simulations on the ISCAS 85 benchmark circuits. The proposed method outperforms previous methods in terms of both accuracy and computational complexity.