• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.93-100
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• 2004

Test scheduling of SoC (System-on-a-chip) is very important because it is one of the prime methods to minimize the testing time under limited power consumption of SoC. In this paper, a heuristic algorithm, in which test resources are selected for groups and arranged based on the size of product of power dissipation and test time together with total power consumption in core-based SoC is proposed. We select test resource groups which has maximum power consumption but does not exceed the constrained power consumption and make the testing time slot of resources in the test resource group to be aligned at the initial position in test space to minimize the idling test time of test resources. The efficiency of proposed algorithm is confirmed by experiment using ITC02 benchmarks.

• Korean Journal of Materials Research
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• v.16 no.2
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• pp.99-105
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• 2006

This paper reports an improved bonding method using the IPA (isopropyl alcohol) assisted low-temperature bonding process for the PMMA (polymethylmethacrylate) micro CE (capillary electrophoresis) chip. There is a problem about channel deformations during the conventional processes such as thermal bonding and solvent bonding methods. The bonding test using an IPA showed good results without channel deformations over 4 inch PMMA wafer at $60^{\circ}C$ and 1.3 bar for 10 minutes. The mechanism of IPA bonding was attributed to the formation of a small amount of vaporized acetone made from the oxidized IPA which allows to solvent bonding. To verify the usefulness of the IPA assisted low-temperature bonding process, the PMMA micro CE chip which had a $45{\mu}m$ channel height was fabricated by hot embossing process. A functional test of the fabricated CE chip was demonstrated by the separation of fluorescein and dichlorofluorescein. Any leakage of liquids was not observed during the test and the electropherogram result was successfully achieved. An IPA assisted low-temperature bonding process could be an easy and effective way to fabricate the PMMA micro CE chip and would help to increase the yield.

• Journal of the Semiconductor & Display Technology
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• v.5 no.1 s.14
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• pp.5-11
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• 2006

One of the most important is to insure that a new circuit design is qualified far release before it is scheduled for manufacturing, test, assembly and delivery. Due to various causes, there happens to be a low yield in the wafer process. Wafer test is a critical process in analyzing the chip characteristics in the EDS(electric die sorting) using analytic tools -wafer map, wafer summary and datalog. In this paper, we propose new analytic map algorithms for DDI chip test data. Using the proposed analytic map algorithms, we expect to improve the yield, quality and analysis time.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.4
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• pp.1-10
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• 2015

The light emitting diodes(LED) package of new structure is proposed to promote the reliability and lifespan by maximize heat dissipation occurred on the chip. We designed and fabricated the LED packages mixing the advantages of chip on board(COB) based on conventional metal printed circuit board(PCB) and the merits of Si sub-mount using base as a substrate. The proposed LED package samples were selected for the superior efficiency of the material through the sealant properties, chip characteristics, and phosphor properties evaluations. Reliability test was conducted the thermal shock test and flux rate according to the usage time at room temperature, high-temperature operation, high-temperature operation, high-temperature storage, low-temperature storage, high-temperature and high-humidity storage. Reliability test result, the average flux rate was maintained at 97.04% for each items. Thus, the Si sub-mount based LED package is expected to be applicable to high power down-light type LED light sources.

• The Journal of the Korea Contents Association
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• v.5 no.1
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• pp.229-236
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• 2005

Testing time and power consumption during testing System-On-a-Chip (SOC) are becoming increasingly important as the IP core increases in a SOC. We present a new algorithm to reduce the scan-in power and test data volume using the modified scan latch reordering. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.67-74
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• 2011

Keys to high wiring density semiconductor packages include flip-chip bonding and build-up substrate technologies. The current issues are the establishment of a fine pitch flip-chip bonding technology and a low coefficient of thermal expansion (CTE) substrate technology. In particular, electromigration and thermomigration in fine pitch flipchip joints have been recognized as a major reliability issue. In this paper, electromigration and thermomigration in Cu/Sn-3Ag-0.5Cu (SAC305)/Cu flip-chip joints and electromigration in Cu/In/Cu flip chip joints are investigated. In the electromigration test, a large electromigration void nucleation at the cathode, large growth of intermetallic compounds (IMCs) at the anode, a unique solder bump deformation towards the cathode, and the significantly prolonged electromigration lifetime with the underfill were observed in both types of joints. In addition, the effects of crystallographic orientation of Sn on electromigration were observed in the Cu/SAC305/Cu joints. In the thermomigration test, Cu dissolution was accelerated on the hot side, and formation of IMCs was enhanced on the cold side at a thermal gradient of about $60^{\circ}C$/cm, which was lower than previously reported. The rate of Cu atom migration was found comparable to that of electromigration under current conditions.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.284-287
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• 2001

In this paper, we designed and implemented a precise pulse motor control chip that generates the parabolic speed pattern. This chip can control step motor[1], DC servo[2] and AC servo motors at high speed and precisely. It can reduce the mechanical vibration to the minimum at the change point of a degree of acceleration. Because the parabolic speed pattern has the continuous acceleration change. In this paper, we present the pulse generation algorithm and the parabolic pattern speed generation. We verify these algorithm using visual C++. We designed this chip with VHDL(Very High Speed Integrated Circuit Hardware Description Language) and executed a logic simulation and synthesis using Synopsys synthesis tool. We executed the pre-layout simulation and post-layout simulation with Verilog-XL simulation tool. This chip was produced with 100 pins, PQFP package by 0.35 um CMOS process and implemented by completely digital logic. We developed the hardware test board and test program using visual C++. We verify the performance of this chip by driving the servo motor and the function by GUI(Graphic User Interface) environment.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.42-49
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• 2013

A simultaneous bidirectional inductively-coupled link is presented. In the conventional inductively-coupled link, data can be bidirectionally transmitted through channel, however not simultaneously. We propose simultaneous bidirectional link for higher data rate with effective echo cancellation technique. Each chip performs TX-mode and RX-mode simultaneously. Instead chip stacking for test, similar test enviroment is realized in a single chip that is fabricated in a $0.13-{\mu}m$ standard CMOS technology.

• The Korean Journal of Cytopathology
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• v.19 no.2
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• pp.119-125
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• 2008

This study was performed to compare the efficacy between a DNA chip method and a Hybrid-Capture II assay (HC-II) for detecting human papillomavirus in patients with intraepithelial lesions of the uterine cervix. From May, 2005, to June, 2006, 192 patients with abnormal colposcopic findings received cervical cytology, HC-II and HPV DNA chip tests, and colposcopic biopsy or conization. We compared the results of HC-II and HPV DNA chip in conjunction with liquid based cervical cytology (LBCC) and confirmed the results of biopsy or conization. The sensitivity of the HPV DNA chip test was higher than HC-II or LBCC. The HPV DNA chip in conjunction with LBCC showed higher sensitivity than any single method and higher sensitivity than HC-II with LBCC. We confirmed that the HPV DNA chip test was more sensitive for detecting HPV in cervical lesions than HC-II, and that it would provide more useful clinical information about HPV type and its multiple infections.

• Journal of the Korea Society of Computer and Information
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• v.21 no.5
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• pp.65-71
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• 2016

Bluetooth technology(BT) is a standard for short distance wireless communication and widely used to connect and control various electronic and telecommunication devices without wires, where CSR8670 chip is generally adopted. These BT devices are required to comply with BT specification and the equipments for conformance test are also important. However, the existing BT testing methods have inconvenience in that they are mostly time-consuming procedure due to not only repetitive execution for each evaluation element but also error-prone nature of manual experiments. This paper proposes an automated BT communication test method using CSR8670 chip, which solves the problems related to manual testing methods. The proposed method can reduce the development period of BT products and guarantee the quality improvement owing to the exact system error detection capability.