• Biotechnology and Bioprocess Engineering:BBE
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• v.9 no.2
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• pp.132-136
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• 2004

The LAL (Limulus amebocyte lysate) test for the detection and quantification of endotoxin is based on the gelation reaction between endotoxin and LAL from a blood extract of Limulus polyphemus. The test is labor intensive, requiring dedicated personnel, a relatively long reaction time (approximately 1 h), relatively large volumes of samples and reagents and the detection of the end-point is rather subjective. To solve these problems, a miniaturized LOC (lab-on-a-chip) prototype, 62mm (L) ${\times}$ 18 mm (W), was fabricated using PDMS (polydimethylsiloxane) bonded to glass. Using this prototype, in which 2mm (W) ${\times}$ 44.3mm (L) ${\times}$ 100 $\mu\textrm{m}$ (D) microfluidic channel was constructed, turbidometric and chromogenic assay detection methods were compared, and the chromogenic method was found the most suitable for a small volume assay. In this assay, the kinetic-point method was more accurate than the end-point method. The PDMS chip thickness was found to be minimized to around 2 mm to allow sufficient light transmittance, which necessitated the use of a glass slide bonding for chip rigidity. Due to this miniaturization, the test time was reduced from 1 h to less than 10 min, and the sample volume could be reduced from 100 to ca. 4.4 ${\mu}$L. In summation, this study suggested that the LOC using the LAL test principle could be an alternative as a semi-automated and reliable method for the detection of endotoxin.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.12
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• pp.1710-1715
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• 2014

In this paper, we propose a novel on-chip test logic for TSV fault detection in 3-dimensional integrated circuits. The proposed logic called OTT realizes the input signal delay-based TSV test method introduced earlier. OTT only includes one F/F, two MUXs, and some additional logic for signal delay. Thus, it requires small silicon area suitable for TSV testing. Both pre-bond and post-bond TSV tests are able to use OTT for short or open fault as well as small delay fault detection.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.271-274
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• 2003

This paper presents a Built-in Current Sensor that detect defects in CMOS integrated circuits using the current testing technique. This scheme employs a cross-coupled connected PMOS transistors, it is used as a current comparator. Our proposed scheme is a negligible impart on the performance of the circuit undo. test (CUT). In addition, in the normal mode of the CUT not dissipation extra power, high speed detection time and applicable deep submicron process. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects. The entire area of the test chip is $116{\times}65{\mu}m^2$. The BICS occupies only $41{\times}17{\mu}m^2$ of area in the test chip. The area overhead of a BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix $0.35{\mu}m$ 2-poly 4-metal N-well CMOS technology.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1556-1557
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• 2007

LCD BLU에 광원의 수명을 측정하고, 고장모드를 분석하기 위해서는 광원을 구성하고 있는 각각의 성분 중에서 광원 자체를 구성하고 있는 R/G/B 광원에 대한 Burn-in test 및 고장모드를 분석하였다. LCD BLU에 있어서 R/G/B LED광원의 역할은 BLU 자체의 수명과 성능에 가장 큰 영향을 미친다. 서로 각각 사용조건하에서의 수명과 성능의 차이에 따라서 BLU 자체의 수명이 결정된다. 이를 평가가기 위해 LED device에 대한 가속수명테스트를 위한 Burn-in test를 실시하였으며, 발생한 고장모드를 분석하였다. 분석결과 누설전류 증가로 인한 불량이 주로 발생하였다. 누설전류 증가를 평가하기 위해 Photo emission microscope(PHEMOS-1000, MoDooTEK Inc.)을 이용하여 저전류에서의 LED chip의 누설전류에 의한 발광을 관찰함으로 인해, LED chip의 신뢰성 및 평가 기준이 됨을 알 수 있다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.9
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• pp.114-120
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• 1995

It is important to test the various kinds of interconnect faults between chips on a card/module. When boundary scan design techniques are adopted, the chip to chip interconnection test generation and application of test patterns is greatly simplified. Various test generation algorithms have been developed for interconnect faults. A new interconnect test generation algorithm is introduced. It reduces the number of test patterns by half over present techniques. It also guarantees the complete diagnosis of mutiple interconnect faults.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2000.10a
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• pp.279-284
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• 2000

The object of this paper is to evaluate the chip breakability using the experimental equation of surface roughness, which is developed in turning by an orthogonal array method. L$\sub$9/(3$^4$) orthogonal array method, one of fractional factorial design has been used to study effects of main cutting parameters such as cutting speed, feed rate and depth of cut, on the surface roughness. The evaluation of chip breakability is used the chip breaking index(C$\sub$B/), non-dimensional parameter. And the analysis of variance (ANOYA)-test has been used to check the significance of cutting parameters. Using the result of ANOYA-test, the experimental equation of chip breakability, which consists of significant cutting parameters, has been developed. The coefficient of determination of this equation is 0.866.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1089-1095
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• 2005

This paper presents a new low-cost Built-In Self-Test (BIST) circuit for 50Hz low noise amplifier (LNA). The BIST circuit is designed for system-on-chip (SoC) transceiver environment. The proposed BIST circuit measures the LNA specifications such as input impedance, voltage gaih, noise figure, and input return loss all in a single SoC environment.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.45-52
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• 2011

It is known that test methods to evaluate solder joint reliability are die shock test, die shear test, 3points bending test, and thermal shock test. The present study investigated the effects of failure mode on 3 types (as-reflowed, $85^{\circ}C$/85%RH treatment, and $150^{\circ}C$/10hr aging) of solder joints for flip-chip BGA package by using various test methods. The test methods and configurations are reported in detail, i.e. die shock, die shear, 3points bending, and thermal shock test. We focus on the failure mode of solder joints under various tests. The test results indicate that die shock and die shear test method can reveal brittle fracture in flip-chip ball grid array (FCBGA) packages with higher sensitivity.

• Journal of the Korean Society of Industry Convergence
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• v.4 no.2
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• pp.127-132
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• 2001

In turning, the chip may be produced in the form of continuous chip or discontinuous chip. The continuous chips are dangerous to the operator and difficult to be handled at high speed machining. The signal of AE(Acoustic Emission) is found out to be related to cutting conditions, tool materials, test conditions and tool geometry in turning. In this study, the relationship between AE signal and chip form was experimentally investigated. The experimental results show that the types of chip form are possible to be classified from the AE signal using fuzzy logic.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.07a
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• pp.127-133
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• 2001

Package reliability test was conducted to investigate the effect of solder composition on ball fatigue strength. The specimens are first assembled using eutectic Composition S $n_{62}$P $b_{36}$A $g_2$, S $n_{63}$P $b_{34.5}$A $g_2$S $b_{0.5}$ solder and Pre-conditioned at MRT Lv 2a and then conducted under Temperature Cycle test(TC). For each case, the ball shear strength is obtained and micro structure photos are taken. SEM and EDX are used to analyze failure mechanism. The degradation of shear strength of solder balls after reliability test is discussed.d.