• 한국신뢰성학회지:신뢰성응용연구
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• 제5권2호
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• pp.221-239
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• 2005

General chip SMD parts(chip resistance, chip capacitor, chip varistor etc.) are very wide used electronics parts for IT units. But, failure modes are indistinct for these chip parts. In factory and field the failure modes are recognized to accidental failure mode caused by potential defect. In this paper used chip varistor ALT(Accelerate Life Test) test for verify general failure modes in chip SMD parts. Also the results are useful for general chip SMD ALT tests.

• 한국신뢰성학회:학술대회논문집
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• 한국신뢰성학회 2005년도 학술발표대회 논문집
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• pp.51-67
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• 2005

General chip SMD parts(chip resistance, chip capacitor, chip varistor etc.) are very wide sed electronics parts for IT units. But, failure modes are indistinct for these chip parts. In factory and field the failure modes are recognized to accidental failure mope caused by potential defect. In this paper used chip varistor ALT(Accelerate Life Test) test for verify general failure modes in chip SMD parts. Also the results are useful for general chip SMD ALT tests.

• 한국산학기술학회논문지
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• 제12권4호
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• pp.1509-1514
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• 2011

IT 제품의 핵심 전자부품에는 MLCC, chip inductors, chip Varistors 등이 있다. chip의 전기적 특성을 검사하기 위해 리노핀을 이용한 접촉검사 방식이 사용되고 있다. 리노핀을 이용한 칩 검사에 고속으로 구동할 수 있는 Actuator가 필요하다. 그 중 PZT Actuator는 압전소자를 이용한 마이크로 Actuator의 하나로 높은 분해능 및 좋은 응답성 그리고 큰 힘을 낼 수 있는 장점을 가지고 있다. 하지만 진동변위가 매우 작다는 단점이 있다. 그래서 이러한 단점을 극복하기 위하여 변위 증폭구조를 설계하는 연구가 활발히 진행되고 있다. 따라서 본 논문에서는 유연힌지를 이용한 지레구조 증폭기구를 설계하였으며, 반도체칩 검사장비 산업분야에서 성능검사 및 전기적 특성을 측정할 수 있는 리노핀용 고속구동 Actuator 시스템을 개발하였다.

• KSBB Journal
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• 제18권5호
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• pp.429-433
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• 2003

LAL 측정용 chip을 제작하기 위해서 우선 시료의 부피 감소에 대한 비탁법과 비색법을 비교하였다. 비색법은 낮은 부피에서 높은 감도를 보여 주었으며 시료의 부피와 무관하게 같은 endotoxin의 농도에서는 같은 흡광도를 보인다는 결론을 얻었다. Endotoxin의 농도에 따른 표준곡선을 end point법과 kinetic point법을 비교한 결과 대한약전의 기준에 적합한 kinetic point법이 적합하였다. 이러한 기초 실험결과를 통해 PDMS LOC를 제작하여 LAL 시험을 수행하였다. LOC를 이용하여 더 짧은 시간과 더 작은 시료로 시험이 가능하도록 하였다. 특히 PDMS LOC는 복잡한 channel을 쉽게 만들 수 있을 뿐 아니라 mold를 이용하여 상용화를 위한 대량 생산이 가능하다. 따라서 PDMS를 이용한 LOC의 제작과 실험을 통해 기존의 수작업의 LAL 시험을 LOC를 이용한 다중시료 측정과 자동화의 가능성을 제시하였다.

• 한국전기전자재료학회논문지
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• 제19권9호
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• pp.825-831
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• 2006

As an increase of chip complexity and level of chip integration, chip input/output (I/O) pad pitches are also drastically reduced. With arrival of high complexity SoC (System on Chip) and SiP (System in Package) products, conventional horizontal type probe card showed its limitation on probing density for wafer level test. To enhance probing density, we proposed new vertical type probe card that has the $70{\mu}m$ probe needle with tungsten wire in $80{\mu}m$ micro-drilled hole in ceramic board. To minimize alignment error, micro-drilling conditions are optimized and epoxy-hardening conditions are also optimized to minimize planarity changes. To apply wafer level test for target devices (T5365 256M SDRAM), designed probe card was characterized by probe needle tension for test, contact resistance measurement, leakage current measurement and the planarity test. Compare to conventional probe card with minimum pitch of $50{\sim}125{\mu}m\;and\;2\;{\Omega}$ of average contact resistance, designed probe card showed only $22{\mu}$ of minimum pitch and $1.5{\Omega}$ of average contact resistance. And also, with the nature of vertical probing style, it showed comparably small contact scratch and it can be applied to bumping type chip test.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
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• pp.924-927
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• 2003

In this paper, we design the memory tester chip set playing an important role in the memory tester as central parts. Memory tester has the sixteen inner instructions to control the test sequence and the address and data signals to DUT. These instructions are saved in memory with each chip such as sequence chip and address/data generator chip. Sequence chip controls the test sequence according to instructions saved in the memory. And Generator chip generates the address and data signals according to instructions saved in the memory, too.

• 대한의생명과학회지
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• 제11권1호
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• pp.51-56
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• 2005

The detection of high-risk human papilloma virus (HPV) allows us to predict the presence and future development of cervical intraepitheliallesion. In this study, we compared Hybrid Capture II and DNA chip methods for detection of HPV in cervical swab samples. And we evaluated the clinical efficacy and diagnostic performance of HPV DNA chip and Hybrid Capture II for detecting HPV in cervical neoplastic lesions. Seventy four patients were classified into three groups according to their histologic diagnosis: Group I (nonspecific chronic cervicitis), Group II (low-grade squamous intraepithelial lesion (SIL); koilocytosis, and mild dysplasia), and Group III (high-grade SIL;, moderate, severe dysplasia and in situ carcinoma). Cytologic diagnosis were based on the Bethesda System. Hybrid Capture II and DNA chip methods were performed to detect HPV. In 41 of the 74 cervical samples $(55.4\%)$, HPV DNAs were detected by Hybrid Capture II. In Group III, HPV-positive cases were detected in 15 $(20.3\%)$ of 74 patients by Hybrid Capture II. 25 patients with ASCUS cytology were histopathologically examined: 9 cases $(36\%)$ were Group II. In 18 patients with low-grade SIL cytology, 13 cases $(72.2\%)$ were Group II and 3 cases $(16.7\%)$ were Group III. 12 cases $(92.3\%)$ were Group ill of 13 patients with high-grade SIL cytology. The sensitivity of each test was $82\%$ in Hybrid Capture II and $53.9\%$ in DNA chip test. And the specificity was $74.3\%,\;85.7\%$ in Hybrid Capture II and DNA chip. In conclusion, Hybrid Capture II test is more sensitive than DNA chip in detecting women with cervical neoplastic lesions. Especially, in diagnosing of ASCUS, Hybrid Capture II test is more sensitive. Therefore, Hybrid Capture II test for cancer-associated HPV DNA is a viable option in the management of women with ASCUS.

• 디지털콘텐츠학회 논문지
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• 제13권4호
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• pp.491-500
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• 2012

본 논문에서는 RF 송수신 시스템 칩 내부의 저잡음증폭기(LNA)와 전체 송수신기 시스템 테스트에 효과적인 새로운 루프백(Loopback) BIST 구조를 제안한다. 제안하는 테스트기법은 외부 테스트장비(Automatic Test Equipment)를 사용하는 기존의 테스트기법과 달리 테스트 모드에서 칩에 내장된 베이스밴드 프로세서를 테스터로 사용하므로써 테스트인가와 테스트평가등을 효율적으로 수행할 수 있는 장점을 갖는다. 높은 주파수의 테스트 출력신호는 낮은 주파수로 변환하여 베이스밴드 프로세서에서 평가하게 됨으로써 테스트용이도가 향상될 수 있다. 제안하는 테스트기법은 ATE와 같은 외부테스트장비의 필요를 최소화하고 테스트 시간과 비용을 줄여 결과적으로 칩 제조비용의 절감을 가능하게 해준다.

• 대한전자공학회논문지SD
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• 제45권2호
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• pp.61-68
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• 2008

본 논문에서는 Advanced Microcontroller Bus Architecture(AMBA) 기반 System-on-Chip(SoC) 테스트를 위한 임베디드 코어 테스트 래퍼를 제시한다. IEEE 1500 과의 호환성을 유지하면서 ARM의 Test Interface Controller(TIC)로도 테스트가 가능한 테스트 래퍼를 설계한다. IEEE 1500 래퍼의 입출력 경계 레지스터를 테스트 패턴 입력과 테스트 결과 출력을 저장하는 임시 레지스터로 활용하고 변형된 테스트 절차를 적용함으로써 Scan In과 Scan Out 뿐만 아니라 PI 인가와 PO 관측도 병행하도록 하여 테스트 시간을 단축시킨다.

• 한국도로학회논문집
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• 제15권2호
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• pp.65-71
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• 2013

PURPOSES : The objective of this study is to evaluate the effect of physical characteristics of emulsion asphalt and aggregate on performance of chip seal pavements. METHODS : In order to evaluate the performance of chip seal materials, the sweep tests and Vialit Plate Shock tests were conducted on the mixtures with five emulsion asphalt binders and three aggregate types. The sweep tests was intended to investigate the change of bonding properties between emulsion asphalt and aggregate with curing time. The Vialit Plate Shock test was used to evaluate the bonding properties of chip seal materials at low temperatures. RESULTS : Results from sweep tests showed that polymer modified emulsion asphalt can reduce the curing time by 1.5 hour comparing with typical emulsion asphalt. It is also found that the Flakiness Index of aggregates and absorption rate of binder are the major factors affecting the bonding properties of chip seal materials. The Vialit Plate Shock test results showed that the average aggregate loss of CRS-2 is ten times higher than CRS-2P No.2 indicating that the use of polymer additives in emulsion asphalt can improve the performance of chip seal materials in low temperature region. CONCLUSIONS : The use of polymer in emulsion asphalt can decrease the curing time of chip seal materials and increase the bonding properties between aggregates and asphalt binder. It is also concluded that the lower Flakiness Index and absorption rate of aggregates can improve the performance of chip seal pavement.