• KSBB Journal
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• v.28 no.4
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• pp.254-259
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• 2013

Herein we present a diagnostic paper chip that can quantitatively detect albumin without external electronic reader and dispensing apparatus. We fabricated a diagnostic paper chip device by printing wax barrier on the paper and wicking it with citrate buffer and tetrabromophenol blue to detect albumin in sample solution. The paper chip is so simple that we dropped a sample solution at sample pad and measure the ratio of two travel distances of the sample solvent and albumin under the name of retention factor. Our result confirmed that the retention factor was constant in the samples with same concentration of albumin and useful determinant for the measurement of albumin concentration. The paper chip is affordable and equipment-free, and close to ideal point-of-care test in accordance with the assured criteria, outlined by the World Health Organization. We assume that this diagnostic paper chip will expand the concept of colorimetric determination and provide a inexpensive diagnostic method to aging society and developing country.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2009.10a
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• pp.67-68
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• 2009

• International Journal of Aerospace System Engineering
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• v.1 no.1
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• pp.44-47
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• 2014

This study proposes a development for the nano silver adhesive, which is applicable to high efficiency LED(light-emitting diode) light. The important issue of LED light is heat exhaust from LED. Generally, the middle area of LED light is increased up to 380K. Therefore, the bottleneck between LED chip and heat sink are caused by high temperature. In this work, the adhesive material between LED Chip and heat sink was newly developed for improvement of bottleneck. The nano silver was adopted to solve heat problem of chip on board package for LED light. In order to evaluate the performance of the nano silver adhesive, the thermal analysis was performed. Moreover both adhesive performance and heat exhaust were verified through the prototype test. From the experimental test results, it is found that the developed nano silver adhesive has the high performance.

• Proceedings of the KWS Conference
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• 2006.05a
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• pp.21-23
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• 2006

The microstructural investigation and thermo-mechanical reliability evaluation of the Sn-3.0Ag-0.5Cu solder bumped flip chip package were carried out during the thermal shock test of the package. In the initial reaction, the reaction product between the solder and Cu mini bump of chip side was Cu6Sn5 layer, while the two phases which were (Cu,Ni)6Sn5 and (Ni,Cu)3Sn4 were formed between the solder and Ni-P layer of the package side. The cracks were occurred at the corner solder joints after the thermal shocks of 400 cycles. The primary failure mechanism of the solder joints in this type of package was confirmed to be thermally activated solder fatigue failure.

• Journal of the Korean Society of Industry Convergence
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• v.2 no.2
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• pp.139-146
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• 1999

Combustion Characteristics of the wood chips(balsa chips) were experimental studied as fundamental investigation of the thermal recycle system of the urban dust. The urban dust contains plastics vegetable and lot of wood material. Then, a wood was chosen as an example of the component of urban dust. A small wood chip was burned in a electric furnace and mass reduction rate during volatile and combustion states were recorded by the micro-electric balance and the combustion flame shape took a photograph by video camera at the mass of wood chips and ambient temperature in the furance. Ignition delay took the minimum value when the mass of the test chip was 0.3g. When a mass of the test chip was smaller then 0.001g, combustion with flame did not burnt.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.892-895
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• 2011

Power consumption during testing System-On-Chip (SOC) are becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

• Journal of Ocean Engineering and Technology
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• v.11 no.1
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• pp.106-112
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• 1997

This paper describes the development of a test-bed vehicle named TAUV which can be a tool to evaluate the performance of a new control algorithm, operating software and the characteristics of sensors for an AUV. The test-bed AUV is designed to operate at depth of ten meters. It is 19.5kg in air and neural buoyancy in water and the dimension is $535{\times}400{\times}102mm$. TAUV is equipped with a magnetic compass, a biazial inclinometer, a rate gyro, a pressure sensor and an altitude sonae for measuring the motion of the vehicle. Two horizoltal thursters and two elevators are installed in order to propel and control the AUV. This paper persents the control system of TAUV which is based on a 16 bit single-chip microprocessor, 80c196kc, and the software architecture for the operating system. Experimental results are included to verify the performance of the TAUV.

• ETRI Journal
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• v.36 no.2
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• pp.293-300
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• 2014

As the system-on-chip (SoC) design becomes more complex, the test costs are increasing. One of the main obstacles of a test cost reduction is the limited number of test channels of the ATE while the number of pins in the design increases. To overcome this problem, a new test architecture using a channel sharing compliant with IEEE Standard 1149.1 and 1500 is proposed. It can significantly reduce the pin count for testing a SoC design. The test input data is transmitted using a test access mechanism composed of only input pins. A single test data output pin is used to measure the sink values. The experimental results show that the proposed architecture not only increases the number of sites to be tested simultaneously, but also reduces the test time. In addition, the yield loss owing to the proven contact problems can be reduced. Using the new architecture, it is possible to achieve a large test time and cost reduction for complex SoC designs with negligible design and test overheads.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.100-103
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• 2008

In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800k gate counts using Charterd 0.18um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.1
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• pp.19-26
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• 2007

This study was focused on the feasibility of ultrasonic bonding of Au flip chip bumps for a practical complementary metal oxide semiconductor (CMOS) image sensor with electroplated Au substrate. The ultrasonic bonding was carried out with different bonding pressures and times after the atmospheric pressure plasma cleaning, and then the die shear test was performed to optimize the ultrasonic bonding parameters. The bonding pressure and time strongly affected the bonding strength of the bumps. The Au flip chip bumps were successfully bonded with the electroplated Au substrate at room temperature, and the bonding strength reached approximate 73 MPa under the optimum conditions.