• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.376-379
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• 2001

In this paper, I design the control chip that controls inner test sequence of Logic Tester to test chip. Logic tester has the thirteen inner instructions to control test sequence in test. And these instructions are saved in memory with test pattern data. Control chip generates address and control signal such as read, write signal of memory. Before testing, necessary data such as start address, end address, etc. are written to inner register of control chip. When test started, control chip receives the instruction in start address and executes, and generates address and control signals to access tester' inner memory. So whole test sequence is controlled by making the address and control signal in tester's inner memory. Control chip designs instruction's execution blocks, respectively. So if inner instruction is added from now on, a revision is easy. The control chip will be made using FPGA of Xilinx Co. in future.

• Biomedical Science Letters
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• v.21 no.1
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• pp.32-39
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• 2015

High-risk (HR) human papillomavirus (HPV) genotypes are strongly associated with cervical cancer, whereas other HPV genotypes are not. To identify the various HPV genotypes in clinical samples, we conducted HPV genotyping using a DNA chip test and reverse blot hybridization assay (REBA) in normal cytology samples and atypical squamous cells of undetermined significance (ASCUS) cytology samples. We also investigated the HPV infection rate and HPV genotype prevalence in women with normal cytology and ASCUS cytology. Liquid-based cytology preparations were used for the initial screening of 205 subjects with normal cytology and ASCUS cytology. The HPV infection rate was 49.8% when using the DNA chip assay and 61.0% when using the REBA test. In patients with normal cytology, the HR-HPV positive rate was 21.9% with the DNA chip assay and 43.9% with the REBA test. In contrast, 8.3% of patients with ASCUS were HR-HPV positive when using the DNA chip assay, and 13.6% were positive when tested with the REBA test. The infection rate of HR-HPV in the 40~50-year age group was significantly higher than that of the other age groups. Based on the cytological analysis of the normal and ASCUS samples, the five most prominent HPV genotypes were HPV 16, 18, 68, 33, and 58 using the DNA chip test, and they were HPV 16, 18, 53, 33, and 66 when using the REBA test. In conclusion, the findings show that the results of the REBA test are comparable to those of the DNA chip test. Most strikingly, the REBA test detected the HR-HPV genotype associated with cervical carcinoma similar to that detected with the DNA chip method. Therefore, the REBA test is a useful method to detect clinically important HR-HPV genotypes.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.1663-1667
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• 2003

This thesis is on tile development of LD(Laser Diode) chip tester and the control system based on graphical programming language(LabVIEW) to control the equipment. The LD chip tester is used to test the optic power and the optic spectrum of the LD Chip. The emitter size of LD chip and the diameter of the receiver(optic fiber) are very small. Therefore, in order to test each chip precisely, this tester needs high accuracy. However each motion part of the tester could not accomplish hish accuracy due to the limit of the mechanical performance. Hence. an image processing with machine vision was carried out in order to compensate for the error. and also a load test was carried out so as to reduce tile impact of load on chip while the probing motion device is working. The obtained results were within ${\pm}$5$\mu\textrm{m}$ error.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.3
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• pp.437-443
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• 2007

In this paper, we propose the power-aware test framework for Network-on-Chip, which is based on embedded processor and on-chip network. First, the possibility of using embedded processor and on-chip network isintroduced and evaluated with benchmark system to test the other embeddedcores. And second, a new generation method of test pattern is presented to reduce the power consumption of on-chip network, which is called don't care mapping. The experimental results show that the embedded processor can be executed like the automatic test equipments, and the test time is reduced and the power consumption is reduced up to 8% at the communication components.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1069-1072
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• 1998

Recently the development of design and automation technology and manufacturing method, has reduced the cost of chip, but it becomes more difficult to test IC chip because test technique doesn't keep up with these techniques. In case of IC testing, obtaining test vectors to be able to detect good chip or bad one is very important, but according to increasing complexity, it is very complex and difficult. Another problem is that during testing, there could be capability of physical and electrical damage on chip. Also there is difficulty in synchronization between CUT (circuit under test) and Test equipment〔1〕. Because of these difficulties, built in self test has been proposed. Not only obtaining test vectors but also reducing test time becomes hot issues nowadays. This paper presents a new test BIST(built in self test) method. Proposed BIST implementation reduces test time and obtains high fault coverage. By searching internal nodes in which are inserted test_point_cells〔2〕and allocating TPG(test pattern generation) stages, test length becomes much shorter.

• Journal of the Korean Institute of Intelligent Systems
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• v.23 no.4
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• pp.286-291
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• 2013

In this paper, in-line type flip chip bump 3D inspection equipment, using white light interferometer with large F.O.V., which is aimed to be used in flip chip bump test process is developed. Results of flip chip bump height measurement in many substrates and repeatability test results for the bumps in fixed location of each substrate are shown. Test results from test bench and those from developed flip chip bump 3D inspection equipment are compared and as a result repeatability is improved by reducing the impact of system vibration. A valuation basis for the testing quality of flip chip bump 3D inspection equipment is proposed.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.2
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• pp.201-206
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• 2007

In this paper, we propose the efficient low power test methodology of NoC(Network-on chip) for the test of core-based systems that use this platform. To reduce the power consumption of transferring data through router channel, the scan vectors are partitioned into flits by channel width. The don't cares in unspecified scan vectors are mapped to binary values to minimize the switching rate between flits. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method leads to about 35% reduction in test power.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.1008-1011
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• 2001

The purpose of this paper is to evaluate the chip breakability during turning using the experimental equation, which is developed by an orthogonal array method. The chip breaking index(CB), non-dimensional parameter is used in the evaluation of chip breakability. The analysis of variance(ANOVA)-test has been used to check the significance of cutting parameters. And using the result of ANOVA-test, the experimental equation of chip breakability, which consists of significant cutting parameters, has been developed.

• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.82-87
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• 2020

In this paper, we introduce the novel idea to improve the B/W usage efficiency of on-chip networks used for TAM to test multiple DRAMs. In order to avoid the local bottleneck of test packets caused by an ATE, we make test patterns using microcode-based instructions within ATE and adopt a test bus to transmit test responses from DRAM DFT (Design for Testability) called Test Generator (TG) to ATE. The proposed test platform will contribute to increasing the test economics of memory IC industry.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.763-768
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• 2005

Bare-chip packaging becomes more popular along with the miniaturization of IT components. In this paper, we have studied flip-chip process, and developed automated bonding system. Among the several bonding method, NCP bonding is chosen and batch-type equipment is manufactured. The dual optics and vision system aligns the chip with the substrate. The bonding head equipped with temperature and force controllers bonds the chip. The system can be easily modified for other bonding methods such as ACF In bonding process, the bonding forte and temperature are known as the most dominant bonding parameters. A parametric study is performed for these two parameters. For the test sample, we used standard flip-chip test kit which consists of FR4 boards and dummy flip-chips. The bonding test was performed fur two types of flip-chips with different chip size and lead pitch. The bonding temperatures are chosen between $25^{\circ}C\;to\;300^{\circ}C$. The bonding forces are chosen between 5N and 300N. The bonding strength is checked using bonding force tester. After the bonding force test, the samples are examined by microscope to determine the failure mode. The relations between the bonding strength and the bonding parameters are analyzed and compared with bonding models. Finally, the most suitable bonding condition is suggested in terms of temperature and force.