• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.376-379
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• 2001

In this paper, I design the control chip that controls inner test sequence of Logic Tester to test chip. Logic tester has the thirteen inner instructions to control test sequence in test. And these instructions are saved in memory with test pattern data. Control chip generates address and control signal such as read, write signal of memory. Before testing, necessary data such as start address, end address, etc. are written to inner register of control chip. When test started, control chip receives the instruction in start address and executes, and generates address and control signals to access tester' inner memory. So whole test sequence is controlled by making the address and control signal in tester's inner memory. Control chip designs instruction's execution blocks, respectively. So if inner instruction is added from now on, a revision is easy. The control chip will be made using FPGA of Xilinx Co. in future.

• 대한의생명과학회지
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• 제21권1호
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• pp.32-39
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• 2015

High-risk (HR) human papillomavirus (HPV) genotypes are strongly associated with cervical cancer, whereas other HPV genotypes are not. To identify the various HPV genotypes in clinical samples, we conducted HPV genotyping using a DNA chip test and reverse blot hybridization assay (REBA) in normal cytology samples and atypical squamous cells of undetermined significance (ASCUS) cytology samples. We also investigated the HPV infection rate and HPV genotype prevalence in women with normal cytology and ASCUS cytology. Liquid-based cytology preparations were used for the initial screening of 205 subjects with normal cytology and ASCUS cytology. The HPV infection rate was 49.8% when using the DNA chip assay and 61.0% when using the REBA test. In patients with normal cytology, the HR-HPV positive rate was 21.9% with the DNA chip assay and 43.9% with the REBA test. In contrast, 8.3% of patients with ASCUS were HR-HPV positive when using the DNA chip assay, and 13.6% were positive when tested with the REBA test. The infection rate of HR-HPV in the 40~50-year age group was significantly higher than that of the other age groups. Based on the cytological analysis of the normal and ASCUS samples, the five most prominent HPV genotypes were HPV 16, 18, 68, 33, and 58 using the DNA chip test, and they were HPV 16, 18, 53, 33, and 66 when using the REBA test. In conclusion, the findings show that the results of the REBA test are comparable to those of the DNA chip test. Most strikingly, the REBA test detected the HR-HPV genotype associated with cervical carcinoma similar to that detected with the DNA chip method. Therefore, the REBA test is a useful method to detect clinically important HR-HPV genotypes.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2003년도 춘계학술대회 논문집
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• pp.1663-1667
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• 2003

This thesis is on tile development of LD(Laser Diode) chip tester and the control system based on graphical programming language(LabVIEW) to control the equipment. The LD chip tester is used to test the optic power and the optic spectrum of the LD Chip. The emitter size of LD chip and the diameter of the receiver(optic fiber) are very small. Therefore, in order to test each chip precisely, this tester needs high accuracy. However each motion part of the tester could not accomplish hish accuracy due to the limit of the mechanical performance. Hence. an image processing with machine vision was carried out in order to compensate for the error. and also a load test was carried out so as to reduce tile impact of load on chip while the probing motion device is working. The obtained results were within ${\pm}$5$\mu\textrm{m}$ error.

• 한국산학기술학회논문지
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• 제8권3호
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• pp.437-443
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• 2007

본 논문에서는 임베디드 프로세서 및 네트워크 구조를 기반으로 구성된 NoC(Network-On-Chip)의 저전력 테스트 구조를 제안한다. 임베디드 프로세서와 여러개의 코어로 구성된 네트워크 구조에 벤치마크 회로를 직접 연결하여 테스트 전력소모를 평가하였으며, 각 코어의 테스트 패턴을 저전력 소모가 되도록 매핑하여 테스트 전력소모를 감소시켰다. 또한 임베디드 프로세스 코어를 ATE(Automatic Test Equipment)로 사용하여 테스트 시간을 줄일수 있었다. ISCAS89 벤치마크 회로에 대해서 테스트 시간은 매우 효과적으로 감소되었으며 평균 전력소모는 약 8%가 감소되었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1069-1072
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• 1998

Recently the development of design and automation technology and manufacturing method, has reduced the cost of chip, but it becomes more difficult to test IC chip because test technique doesn't keep up with these techniques. In case of IC testing, obtaining test vectors to be able to detect good chip or bad one is very important, but according to increasing complexity, it is very complex and difficult. Another problem is that during testing, there could be capability of physical and electrical damage on chip. Also there is difficulty in synchronization between CUT (circuit under test) and Test equipment〔1〕. Because of these difficulties, built in self test has been proposed. Not only obtaining test vectors but also reducing test time becomes hot issues nowadays. This paper presents a new test BIST(built in self test) method. Proposed BIST implementation reduces test time and obtains high fault coverage. By searching internal nodes in which are inserted test_point_cells〔2〕and allocating TPG(test pattern generation) stages, test length becomes much shorter.

• 한국지능시스템학회논문지
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• 제23권4호
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• pp.286-291
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• 2013

대시야 백색광간섭계(WSI ; White Light Scanning Interferometer)를 이용하여, Flip Chip Bump 검사 공정에 적용하는 것을 목적으로 한 인라인 형태의 플립칩 범프 3차원 검사 장치를 개발한다. 여러 서브스트레이트에 있는 플립칩 범프 높이 측정 결과와 이에 의한 동일한 여러 범프에 대한 반복성 측정 실험 결과를 제시한다. 테스트 벤치에서의 실험 결과와 개발된 플립칩 범프 3차원 검사 장치에서의 실험 결과를 비교하였으며 진동의 영향이 감소되어 개선된 반복성 실험 결과를 얻을 수 있었다. 플립칩 범프 3차원 검사 장치의 검사성능을 평가할 수 있는 기준을 제시한다.

• 한국산학기술학회논문지
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• 제8권2호
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• pp.201-206
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• 2007

본 논문에서는 NoC(Network-on Chip) 구조로 구현된 core-based 시스템에 대한 효율적인 저전력 테스트 방법을 제안한다 NoC의 라우터 채널로 전송되는 테스트 데이터의 전력소모를 줄이기 위해서 스캔 벡터들을 채널 폭만큼의 길이를 갖는 flit으로 분할하고 nit간 천이율(switching rate)이 최소화 되도록 don't care 입력을 할당하였다. ISCAS 89 벤치마크에 대하여 실험을 한 결과, 제안된 방법은 약 35%의 전력 감소를 나타내었다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2001년도 춘계학술대회 논문집
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• pp.1008-1011
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• 2001

The purpose of this paper is to evaluate the chip breakability during turning using the experimental equation, which is developed by an orthogonal array method. The chip breaking index(CB), non-dimensional parameter is used in the evaluation of chip breakability. The analysis of variance(ANOVA)-test has been used to check the significance of cutting parameters. And using the result of ANOVA-test, the experimental equation of chip breakability, which consists of significant cutting parameters, has been developed.

• 반도체디스플레이기술학회지
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• 제19권2호
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• pp.82-87
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• 2020

In this paper, we introduce the novel idea to improve the B/W usage efficiency of on-chip networks used for TAM to test multiple DRAMs. In order to avoid the local bottleneck of test packets caused by an ATE, we make test patterns using microcode-based instructions within ATE and adopt a test bus to transmit test responses from DRAM DFT (Design for Testability) called Test Generator (TG) to ATE. The proposed test platform will contribute to increasing the test economics of memory IC industry.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 추계학술대회 논문집
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• pp.763-768
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• 2005

Bare-chip packaging becomes more popular along with the miniaturization of IT components. In this paper, we have studied flip-chip process, and developed automated bonding system. Among the several bonding method, NCP bonding is chosen and batch-type equipment is manufactured. The dual optics and vision system aligns the chip with the substrate. The bonding head equipped with temperature and force controllers bonds the chip. The system can be easily modified for other bonding methods such as ACF In bonding process, the bonding forte and temperature are known as the most dominant bonding parameters. A parametric study is performed for these two parameters. For the test sample, we used standard flip-chip test kit which consists of FR4 boards and dummy flip-chips. The bonding test was performed fur two types of flip-chips with different chip size and lead pitch. The bonding temperatures are chosen between $25^{\circ}C\;to\;300^{\circ}C$. The bonding forces are chosen between 5N and 300N. The bonding strength is checked using bonding force tester. After the bonding force test, the samples are examined by microscope to determine the failure mode. The relations between the bonding strength and the bonding parameters are analyzed and compared with bonding models. Finally, the most suitable bonding condition is suggested in terms of temperature and force.