• 제목/요약/키워드: Chip Treatment Equipment

검색결과 10건 처리시간 0.022초

Evaluation of ENEPIG Surface Treatment for High-reliability PCB in Mobile Module

  • Lee, Joon-Kyun;Yim, Young-Min;Seo, Jun-Ho
    • 한국표면공학회지
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    • 제43권3호
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    • pp.142-147
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    • 2010
  • We evaluated characteristics of ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) surface treatment for mobile equipment that requires high reliability, in addition to investigating surface treatment processes for semiconductor boards that require high reliability such as regular PCB-package systems, board-on-chip, chip-scaled package (CSP), etc and application for semiconductor package board of SIP, BOC. As a result, it appeared that ENEPIG has superior properties compared to ENIG surface treatment in corrosion resistance, solder junction, wetting, etc. We anticipate that these results will be able to lend credibility to ENEPIG as a low-cost alternative for producing mobile devices such as the cell phones, especially when applied to mass production.

대형 공작기계용 칩 처리시스템 설계 및 커터 해석 (Analysis of Cutter and Design of Chip Processing System for Large Scale Machine Tool)

  • 이종문;양영준
    • 한국기계가공학회지
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    • 제11권4호
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    • pp.147-153
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    • 2012
  • The demands of the large scale machine tools, for instance, such as planomiller, turning machine, boring machine, NC machine, have been gradually increased in recent years. As the performances of machine tools and/or cutting tools are advanced, it is possible to perform high-speed and high-precision cutting works. The effective treatment of wet chip, which is discharged from cutting works, becomes very important problems. Therefore, this study is forced on the design of large scale machine tools using CATIA V5R18 and analysis of cutter, which is considered as essential equipment in large scale machine tools, using MSC.Nastran & MSC.Patran. Especially, the relations between tolerated load of cutter, driving horse power and rpm of driving shaft in chip processing system are investigated through analysis. As the results, the reliability of design could be improved by evaluating simulated numerical values, it showed that tolerated loads of supported part and edged part of cutter are 87,000N and 14,450N, respectively.

전해질 고분자 코팅 표면을 이용한 세포칩 제작 (Fabrication of Cell Chip through Eco-friendly Process)

  • 정헌호;송환문;이창수
    • 청정기술
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    • 제17권1호
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    • pp.25-30
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    • 2011
  • 본 연구 논문은 수용액 기반의 청정 표면 개질 기술을 이용하여 세포칩을 제작하는 방법에 관한 것이다. 세포칩의 활용범위는 유전학, 의생물학, 세포생물학 등과 같은 기초학문과 더불어 암 진단 및 치료에 대한 유용한 도구로 응용 가능성을 가지게 된다. 기존의 세포 칩 제작을 위해서는 다량의 유기용매의 사용, 반도체 공정의 복잡성, 고가의 장비 등을 사용함으로 인해 경제적 손실과 환경적 악영향을 주었다. 본 연구에서는 수용액 기반의 청정 표면 개질 기술과 마이크로 컨택트 프린팅 방법을 이용한 세포 패터닝 기술을 융합하여 매우 손쉬운 세포 칩 구현을 하는 기반기술을 제시하였다. 이 세포칩을 이용하여 암세포와 정상세포간의 세포표면에서 발현되는 다양한 탄수화물 및 그의 유도체의 발현양의 차이를 분석할 수 있었다. 이를 바탕으로 새로운 암진단 기술 및 기초 의공학 기술에 활용하고자 한다.

고주파용 저온 동시소성 세라믹(LTCC)칩 커플러 제조: I. 전극형성에 대한 결합제 분해공정의 영향 (Fabrication of Low Temperature Cofired Ceramic (LTCC) Chip Couplers for High Frequencies : I, Effects of Binder Burnout Process on the Formation of Electrode Line)

  • 조남태;심광보;이선우;구기덕
    • 한국세라믹학회지
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    • 제36권6호
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    • pp.583-589
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    • 1999
  • In the fabrication of ceramic chip couples for high frequency application such as the mobile communication equipment the formation of electrode lines and Ag diffusion were investigated with heat treatment conditions for removing organic binders. The deformation and densification of the electrode line greatly depended on the binder burnout process due to the overlapped temperature zone near 400$^{\circ}C$ of the binder dissociation and the solid phase sintering of the silver electrode. Ag ions were diffused into the glass ceramic substrate. The Ag diffusion was led by the glassy phase containing Pb ions rather than by the crystalline phase containing Ca ions. The fact suggests that the Ag diffusion could be controlled by managing the composition of the glass ceramic substrate.

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칩 처리가 포함된 절삭유/폐유 분리 및 냉각 시스템 개발 (Development of Coolant/Waste-oil Separating and Cooling System with Chip Treatment)

  • 김중선;이동섭;왕덕현
    • 한국기계가공학회지
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    • 제16권3호
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    • pp.16-23
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    • 2017
  • For most machine tools, it is necessary to remove chips and coolant oil because it they will continue to be created during the manufacture of workpieces. Existing products that are in use are installed and used as they reflect depending on the characteristics of each device separately. This study proposes a method to remove the security chip as well as developing an integrated system capable of reducing coolant damage. The Leverage AutoCAD and CATIA program was used for 2D and 3D design, shapes were identified by utilizing the KeyShot program, and the load and displacement analysis of the development apparatus was performed utilizing the ANSYS program. After the prototype underwent sufficient design review, the mixed oil separation device had a complete sensor control program using the LabVIEW program. The chip design process for transferring experiments and experiments on the mixed oil cooling device were developed for performance tests of the product. The final product resulted in an increase in space utilization during commercialization, reduced installation costs, and caused social effects such as pulmonary flow reduction, which, through the economic costs, reduces pollution, resulting in various benefits to the industry, such as deceased errors in the workplace decreases.

Fine-Pitch Solder on Pad Process for Microbump Interconnection

  • Bae, Hyun-Cheol;Lee, Haksun;Choi, Kwang-Seong;Eom, Yong-Sung
    • ETRI Journal
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    • 제35권6호
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    • pp.1152-1155
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    • 2013
  • A cost-effective and simple solder on pad (SoP) process is proposed for a fine-pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60-${\mu}m$ pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine-pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine-pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45-${\mu}m$ diameter and 60-${\mu}m$ pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and microbump interconnection using a screen printing process.

UV 장비 및 대기압 플라즈마 장비를 이용한 PCB 표면 처리 효과 비교 (Comparison of PCB Surface Treatment Effect Using UV Equipment and Atmospheric Pressure Plasma Equipment)

  • 유선중
    • 마이크로전자및패키징학회지
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    • 제16권3호
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    • pp.53-59
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    • 2009
  • PCB 표면 개질 및 세정에 있어서 저압 수은 램프를 이용한 UV 장비가 널리 사용되어왔다. 본 연구에서는 공정의 생산성을 향상 시키기 위하여 기존 UV 장비를 대체하여 리모트 DBD 방식의 대기압플라즈마 장비를 새로이 개발하였다. 두 장비의 생산성 비교는 처리 시간 증가에 따른 표면 접촉각의 변화를 측정함으로써 정량적으로 비교할 수 있었다. 측정 결과 대기압 플라즈마 장비의 생산성이 UV 장비에 비하여 매우 우수한 것으로 확인 되었다. 또한 XPS를 이용한 표면 조성 측정 결과 동일한 접촉각 수준에서 UV 및 대기압 처리의 효과는 유사한 것으로 파악되었다. 즉, 유기 오염 수준이 감소되었으며 표면 일부 표면 원소가 산회되었다. 최종적으로 대기압 플라즈마를 BGA제조의 플럭스 도포 공정에 적용하였는데, 대기압 플라즈마를 처리함으로써 도포 공정의 균일도가 향상되는 결과를 얻을 수 있었다.

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Surface Treatment of Ge Grown Epitaxially on Si by Ex-Situ Annealing for Optical Computing by Ge Technology

  • Chen, Xiaochi;Huo, Yijie;Cho, Seongjae;Park, Byung-Gook;Harris, James S. Jr.
    • IEIE Transactions on Smart Processing and Computing
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    • 제3권5호
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    • pp.331-337
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    • 2014
  • Ge is becoming an increasingly popular semiconductor material with high Si compatibility for on-chip optical interconnect technology. For a better manifestation of the meritorious material properties of Ge, its surface treatment should be performed satisfactorily before the electronic and photonic components are fabricated. Ex-situ rapid thermal annealing (RTA) processes with different gases were carried out to examine the effects of the annealing gases on the thin-film quality of Ge grown epitaxially on Si substrates. The Ge-on-Si samples were prepared in different structures using the same equipment, reduced-pressure chemical vapor deposition (RPCVD), and the samples annealed in $N_2$, forming gas (FG), and $O_2$ were compared with the unannealed (deposited and only cleaned) samples to confirm the improvements in Ge quality. To evaluate the thin-film quality, room-temperature photoluminescence (PL) measurements were performed. Among the compared samples, the $O_2$-annealed samples showed the strongest PL signals, regardless of the sample structures, which shows that ex-situ RTA in the $O_2$ environment would be an effective technique for the surface treatment of Ge in fabricating Ge devices for optical computing systems.

DNA 염기서열 분석을 위한 전기 화학적 측정법 (Electrochemical measurement for analysis of DNA sequence)

  • 조성보;홍진섭;김영미;박정호
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제51권2호
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    • pp.92-97
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    • 2002
  • One of the important roles of a DNA chip is the capability of detecting genetic diseases and mutations by analyzing DNA sequence. For a successful electrochemical genotyping, several aspects should be considered including the chemical treatment of electrode surface, DNA immobilization on electrode, hybridization, choice of an intercalator to be selectively bound to double standee DNA, and an equipment for detecting and analyzing the output signal. Au was used as the electrode material, 2-mercaptoethanol was used for linking DNA to Au electrode, and methylene blue was used as an indicator that can be bound to a double stranded DNA selectively. From the analysis of reductive current of this indicator that was bound to a double stranded DNA on an electrode, a normal double stranded DNA was able to be distinguished from a single stranded DNA in just a few seconds. Also, it was found that the peak reduction current of indicator is proportional to the concentration of target DNA to be hybridized with probe DNA. Therefore, it is possible to realize a sim71e and cheats DNA sensor using the electrochemical measurement for genotyping.

Novel Low-Volume Solder-on-Pad Process for Fine Pitch Cu Pillar Bump Interconnection

  • Bae, Hyun-Cheol;Lee, Haksun;Eom, Yong-Sung;Choi, Kwang-Seong
    • 마이크로전자및패키징학회지
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    • 제22권2호
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    • pp.55-59
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    • 2015
  • Novel low-volume solder-on-pad (SoP) process is proposed for a fine pitch Cu pillar bump interconnection. A novel solder bumping material (SBM) has been developed for the $60{\mu}m$ pitch SoP using screen printing process. SBM, which is composed of ternary Sn-3.0Ag-0.5Cu (SAC305) solder powder and a polymer resin, is a paste material to perform a fine-pitch SoP in place of the electroplating process. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder; the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. The Si chip and substrate with daisy-chain pattern are fabricated to develop the fine pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si substrate has 6724 under bump metallization (UBM) with a $45{\mu}m$ diameter and $60{\mu}m$ pitch. The Si chip with Cu pillar bump is flip chip bonded with the SoP formed substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of underfill. The optimized interconnection process has been validated by the electrical characterization of the daisy-chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and micro bump interconnection using a screen printing process.