• 한국정밀공학회지
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• 제12권4호
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• pp.135-142
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• 1995

Recently, the analysis of microcutting with submicrometer depth of cut is tried to get a more high quality surface product, but to get a valuable result another method instead of conventional finite element method must be considered because finite element method is impossible for a very small focused region and mesh size. As the alternative method, Molecular Dynamics or Statics is suggested and accepted in the field of microcutting, indentation and crack propagation. In this paper using Molecular Dynamics simulation, the phenomena of microcutting with subnanometer chip thickness is studied and the cutting mechanism for tool edge configuration is evaluated. As the result of simulation the atomistic chip formation is achieved.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(5)
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• pp.171-174
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• 2000

In stead of RF module which has been used conventionally in many remote measurement applications, a new type of remote measurement system based on PCS(Personal communication system) and one chip Microcontroller is proposed in this work. PCS has many advantages with respect to cost reliability, communication quality, and so on. The proposed system consists of three different modules: PCS module, micro-controller module, and sensor module. System configuration as well as illustrative experiments will be described in detail.

• Journal of electromagnetic engineering and science
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• 제11권4호
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• pp.282-289
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• 2011

GHz electromagnetic interference (EMI) characteristics are analyzed for a 3dimensional (3D) stacked chip power distribution network (PDN) with through silicon via (TSV) connections. The EMI problem is mostly raised by P/G (power/ground) noise due to high switching current magnitudes and high PDN impedances. The 3D stacked chip PDN is decomposed into P/G TSVs and vertically stacked capacitive chip PDNs. The TSV inductances combine with the chip PDN capacitances produce resonances and increase the PDN impedance level in the GHz frequency range. These effects depend on stacking configurations and P/G TSV designs and are analyzed using the P/G TSV model and chip PDN model. When a small size chip PDN and a large size chip PDN are stacked, the small one's impedance is more seriously affected by TSV effects and shows higher levels. As a P/G TSV location is moved to a corner of the chip PDNs, larger PDN impedances appear. When P/G TSV numbers are enlarged, the TSV effects push the resonances to a higher frequency range. As a small size chip PDN is located closer to the center of a large size chip PDN, the TSV effects are enhanced.

• 한국조명전기설비학회지:조명전기설비
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• 제3권2호
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• pp.63-68
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• 1989

정지형 전원(Static Power Supply) 설계를 위한 다중 PAM 인버터에 관하여 논한다. 인버터의 제어부는 원칩 마이크로 컴퓨터(One-chip Microcomputer)로 구성하여 간단히 제어신호를 얻었고, 종단 구성은 더블 브리지 인버터와 3상 3권선 변압기로 구성하였다. 출력 파형은 제어기와 변압기를 이용하여 1주기당 22 스텝의 전압레벨로 다중 PAM파형을 합성하였으며, 저역 여파기(Low Pass Filter)에 의해 정현파에 가까운 파형을 얻었다.

• 전자공학회논문지D
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• 제35D권5호
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• pp.1-10
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• 1998

A GaAs MMIC composed of VCO (voltage controlled oscillator) and mixer for PCS receiver has been developed using 1.mu.m ion implanted GaAs MESFET process. The VCO consists of a colpitts-type oscillator with a dielectric resonator and the circuit configuration of the mixer is a dual-gate type with an asymmetric combination of LO and RF FETs for the improvement of intermodulation characteristics. The common-source self-biasing is used in all circuits including a buffer amplifier and mixer, achieving a single power supply (3V) operation. The total power dissipation is 78mW. The VCO chip shows a phase noise of-99 dBc/Hz at 100KHz offset. The combined VCO/mixer chip shows a flat conversion gain of 2dB, the frequency-tuning factor of 80MHz/volts in the varacter bias ranging from 0.5V to 0.5V , and output IP3 of dBm at varactor bias of 0V. The fabricated chip size is 2.5mm X 1.4mm.

• 전기학회논문지
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• 제56권11호
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• pp.1982-1987
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• 2007

This paper presents the design and analysis of LNA-Mixer for 2.45GHz RFID reader. The LNA is implemented by PCSNIM method for low power consumption. The Mixer is implemented by using the Gilbert-type configuration, current bleeding technique and the resonating technique for the tail capacitance. The connection between the two designed circuits is made by active balun. This LNA-Mixer has about 22dB gain and 8.5dB Noise Figure for -50dBm input RF power, LO power is 0dBm, RF frequency is 2.45 GHz and IF frequency is 100kHz. The layout of LNA-Mixer for one-chip design in a 0.18-um TSMC process has $2.5mm{\times}1.0mm$ size.

• 동력기계공학회지
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• 제18권3호
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• pp.87-92
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• 2014

This study is aimed at investigating the thermal behavior of immersion-cooled high power LED lighting engines. 3D CFD models have been generated for the numerical analysis. Five cases in terms of the configuration of LED chips have been explored for various passive cooling conditions of the lighting engine, i.e., the natural air convection with a lens, the natural air convection without a lens, the deionized water-immersion cooling condition with a lens. The numerical study reveals that the deionized water-immersion cooled lighting engine has nearly twice better thermal performance than the natural air convection cooled lighting engine containing a lens. The investigation has also demonstrated that the four chips configuration has the better thermal performance than the single chip configuration.

• Journal of electromagnetic engineering and science
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• 제12권4호
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• pp.234-239
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• 2012

This paper presents a compact K-band Doppler radar sensor for human vital signal detection that uses a radar configuration with only single coupler. The proposed radar front-end configuration can reduce the chip size and the additional RF power loss. The radar front-end IC is composed of a Lange coupler, VCO, and single balanced mixer. The oscillation frequency of the VCO is from 27.3 to 27.8 GHz. The phase noise of the VCO is -91.2 dBc/Hz at a 1 MHz offset frequency, and the output power is -4.8 dBm. The conversion gain of the mixer is about 11 dB. The chip size is $0.89{\times}1.47mm^2$. The compact Ka-band Doppler radar system was developed in order to demonstrate remote human vital signal detection. The radar system consists of a Ka-band Doppler radar module with a $2{\times}2$ patch array antenna, baseband signal conditioning block, DAQ system, and signal processing program. The front-end module size is $2.5{\times}2.5cm^2$. The proposed radar sensor can properly capture a human heartbeat and respiration rate at the distance of 50 cm.

• 한국전기전자재료학회논문지
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• 제25권9호
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• pp.723-726
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• 2012

A current intensity convertible CLD chip was fabricated using small and large FET cell configuration. Pinch-off current of 8.82 mA and 11.56 mA were obtained for small and large cell in the CLD chip, respectively. Constant current was fairly maintained until the breakdown voltage of 60 V. Measured knee voltage, $V_k$ were 3.8 V and 4.5 V for small and large cell, respectively. We configured current amplifying chip with parallel connection of each cells, by connecting 8 individual large cells in parallel network, 92.0 mA of current was obtained. The pinch-off constant current of CLD chip was varied very linearly with respect to the number of parallel connected cell.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 Proceedings of 6th International Joint Symposium on Microeletronics and Packaging
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• pp.27-34
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• 2001

The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.