• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.11
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• pp.939-945
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• 2002

The rise throughput and the stability in the device fabrication can be obtained by applying chemical mechanical polishing (CMP) process in 0.18 $\mu\textrm{m}$ semiconductor device. However, it still has various problems due to the CMP equipment. Especially, among the CMP components, process variables are very important parameters in determining the removal rate and non-uniformity. In this paper, we studied the DOE (design of experiment) method in order to get the optimized CMP equipment variables. Various process parameters, such as table and head speed, slurry flow rate and down force, have investigated in the viewpoint of removal rate and non-uniformity. Through the above DOE results, we could set-up the optimal CMP process parameters.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1369-1371
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• 2001

This paper describes on thinning SDB SOI substrates by SDB technology and Electro-chemical etch-stop. The surface of the fabricated SDB SOI substrates is more uniform than that grinding or polishing by mechanical method, and this process is possible to accurate SOI thickness control. During Electrochemical etch-stop, leakage current versus voltage curves were measured for analysis of the open current potential (OCP) point and the passivation potential (PP) poin and determinated to anodic passivation potential. The surface roughness and selectively controlled thickness of the fabricated SOI substrates were analyzed by using AFM and SEM, respectively.

• Proceedings of the KIEE Conference
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• 2000.11a
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• pp.250-255
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• 2000

본 "수소 플라즈마를 이용한 SOI 기판 제작 및 SOI 전력용 반도체 소자 제작에 관한 연구"를 통해 수소플라즈마 전처리 공정에 의한 실리콘 기판 표면의 활성화를 통해 실리콘 직접 접합 공정을 수행하여 접합된 기판쌍을 제작할 수 있었으며, 접합된 기판쌍에 대한 CMP(Chemical Mechanical Polishing) 공정을 통해 SOI(Silicon on Insulator) 기판을 제작할 수 있었다. 아울러, 소자의 동작 시뮬레이션을 통해 기존 SOI LIGBT(Lateral Insulated Gate Bipolar Transistor) 소자에 비해 동작 특성이 향상된 이중 채널 SOI LIGBT 소자의 설계 파라미터를 도출하였으며, 공정 시뮬레이션을 통해 소자 제작 공정 조건을 확립하였고, 마스크 설계 및 소자 제작을 통해 본 연구 수행으로 개발된 SOI 기판의 전력용 반도체 소자 제작에 대한 가능성을 확인할 수 있었다.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.481-482
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• 2008

In this paper, the advanced process has been presented to remove the WSix peeling that was made in sub 100nm DRAM SRCAT(Sphere-shaped-Recess-Ch annel-Array Transistor). The source of WSix peeling was proved to be the groove of gate poly film. We have completely solved the problems to adopt the gate-poly CMP (Chemical Mechanical Polishing) process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.105-106
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• 2005

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process has been widely used in microelectronics and semiconductor processes. Indium tin oxide (ITO) thin film was polished by CMP by the change of process parameters for the improvement of CMP performance. Removal rate and planarity were improved after CMP process at the optimized process parameters compared to that before CMP process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.107-108
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• 2005

In this paper, we first applied the chemical mechanical polishing (CMP) process to the planarization of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. $Pb_{1.1}(Zr_{0.52}Ti_{0.48})O_3$ (shortly PZT) ferroelectric film was fabricated by the sol-gel method. And then, we compared the structural characteristics before and after CMP process of PZT films. Their dependence on slurry composition was also investigated. We expect that our results will be useful promise of global planarization for ferroelectric random access memories (FRAM) application in the near future.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.05a
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• pp.239-239
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• 2004

화학적 기계연마 공정(CMP)은 반도체 웨이퍼를 수 천$\AA$m/min의 MRR로 2$\mu\textrm{m}$ 이내의 W(Total Thickness Variable) 조건을 만족시키는 초정밀 광역 평탄화 기술이다. 일반적인 CMP 방법은 서로 다른 회전 중심을 갖고 동일한 방향으로 회전하는 웨이퍼와 다공성 패드 사이에 연마액인 슬러리를 넣어 연마하는 것이다. CMP 공정기술은 1990년 대 중반에 개발되었으나, 아직까지 연마 메커니즘이 완벽하게 밝혀지지 않았다. 따라서 장비를 최적화하기 위해 실험에 의존적일 수밖에 없으나, 이러한 방법은 막대한 자금과 노력뿐만 아니라 상당한 시간을 필요로 하기 때문에, 앞으로 가속될 연마대상 재료의 변화 및 다양한 속도에 발맞출 수 없다.(중략)

• Proceedings of the KIEE Conference
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• 2006.07b
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• pp.1271-1272
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• 2006

CMP(chemical mechanical polishing) process has been attracted as an essential technology of multi-level interconnection. However, the COO(cost of ownership) is very high, because of high consumable cost. Especially, among the consumables, slurry dominates more than 40%. So, we focused how to reduce the consumption of raw slurry. In this paper, $ZrO_2$, $CeO_2$, and $MnO_2$ abrasives were added de-ionized water (DIW) and pH control as a function of KOH contents. We have investigate the possibility of new abrasive for the oxide CMP application.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.05a
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• pp.103-104
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• 2006

In this paper. we first applied the chemical mechanical polishing (CMP) process to the planarization of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interlace. $Pb_{1.1}(Zr_{0.52}Ti_{0.48})O_3$ (shortly PZT) ferroelectric film was fabricated by the sol-gel method. And then. we compared the structural characteristics before and alter CMP process of PZT films. Their dependence on slurry composition was also investigated. We expect that our results will be useful promise of global planarization for ferroelectric random access memories (FRAM) application in the near future.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.540-540
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• 2008

본 논문에서는 KOH 전해액을 이용하여 Cu 막의 부동태층의 형성을 I-V를 통해 평가하였으며, 이를 토대로 최적화된 전압과 시간을 알 수 있었다. 또한, SEM, EDS, XRD를 통해 표면 품질 및 성분 분석을 비교 분석하였다.