• Journal of the Korean Ceramic Society
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• v.49 no.6
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• pp.631-636
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• 2012

Conventional SONOS (poly-silicon/oxide/nitride/oxide/silicon) type memory is associated with a retention issue due to the continuous demand for scaled-down devices. In this study, $Al_2O_3/Y_2O_3/SiO_2$ (AYO) multilayer structures using a high-k $Y_2O_3$ film as a charge-trapping layer were fabricated for nonvolatile memory applications. This work focused on improving the retention properties using a $Y_2O_3$ layer with different tunnel oxide thickness ranging from 3 nm to 5 nm created by metal organic chemical vapor deposition (MOCVD). The electrical properties and reliabilities of each specimen were evaluated. The results showed that the $Y_2O_3$ with 4 nm $SiO_2$ tunnel oxide layer had the largest memory window of 1.29 V. In addition, all specimens exhibited stable endurance characteristics (program/erasecycles up to $10^4$) due to the superior charge-trapping characteristics of $Y_2O_3$. We expect that these high-k $Y_2O_3$ films can be candidates to replace $Si_3N_4$ films as the charge-trapping layer in SONOS-type flash memory devices.

• Transactions on Electrical and Electronic Materials
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• v.15 no.5
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• pp.245-248
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• 2014

$Pt/Al_2O_3/Si_3N_4/SiO_2/Si$ charge trap flash memory structures with various thicknesses of the $Si_3N_4$ charge trapping layer were fabricated. According to the calculated and measured results, we depicted electron loss in a schematic diagram that illustrates how the trap to band tunneling and thermal excitation affects electrons loss behavior with the change of $Si_3N_4$ thickness, temperature and trap energy levels. As a result, we deduce that $Si_3N_4$ thicknesses of more than 6 or less than 4.3 nm give no contribution to improving memory performance.

• The KIPS Transactions:PartA
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• v.15A no.4
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• pp.211-216
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• 2008

In this paper we fabricated and measured the $0.26{\mu}m$ NMOSFET with wet gate oxide and nitride oxide gate to compare that the charateristics of hot carrier effect, charge to breakdown, transistor Id_Vg curve, charge trapping, and SILC(Stress Induced Leakage Current) using the HP4145 device tester. As a result we find that the characteristics of nitride oxide gate device better than wet gate oxide device, especially hot carrier lifetime(nitride oxide gate device satisfied 30 years, but the lifetime of wet gate oxide was only 0.1 year), variation of Vg, charge to breakdown, electric field simulation and charge trapping etc.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.05a
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• pp.107-110
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• 1995

Space charge formation in epoxy/silica composites has been investigated by the pulsed electroacoustic (PEA) method. The addition of silica resulted in homocharge formation, which attributed to the interfacial trapping of injected charge at epoxy/silica interfaces, Homocharge accumulation with increase of voltage and silica content.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.7
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• pp.387-393
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• 2016

Threshold voltage shift has been observed from many thin-film transistors (TFTs) and the time evolution of the shift can be modeled as the stretched-exponential and -hyperbola function. These analytic models are derived from the kinetic equation for defect-creation or charge-trapping and the equation consists of only reversible reactions. In reality TFT's a shift is permanent due to an irreversible reaction and, as a result, it is reasonable to consider that both reversible and irreversible reactions exist in a TFT. In this paper the case when both reactions exist in parallel and make a combined threshold voltage shift is modeled and simulated. The results show that a combined threshold voltage shift observed from a TFT may agrees with the analytic models and, thus, the analytic models don't guarantee whether the cause of the shift is defection-creation or charge-trapping.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1502-1504
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• 1996

The effects of electrical stress in hydrogen passivated and as-fabricated poly-Si TFT's are investigated. It is observed that the charge trapping in the gate dielectric is the dominant degradation mechanism in poly-Si TFT's which has been stressed by the gate bias alone while the creation of defects in the poly-Si film is prevalent in gate and drain bias stressed devices. The degradation due to the gate bias stress is dramatically reduced with hydrogenation time while the degradation due to the gate and drain bias stress is increased a little. From the experimental results, it is considered that hydrogenation suppress the charge trapping at gate dielectrics as well as improve the characteristics of poly-Si TFT's.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.5
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• pp.341-346
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• 2013

Threshold voltage shift caused by trapping and release of charge carriers in a thin-film transistor (TFT) is implemented in AIM-SPICE tool. Turning on and off voltages are alternatively applied to a TFT to extract charge trapping and releasing process. Each process is divided into sequentially ordered processes, which are numerically modeled and implemented in a computer language. The results show a good agreement with the experimental data, which are modeled. Since the proposed method is independent of TFT's behavior models implemented in SPICE tools, it can be easily added to them.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.7
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• pp.1121-1127
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• 1994

The accelerated degradation phenomena in amorphous silicon thin film transistors due to both electrical stress and visible light illumination under the elevated temperature have been investigated systematically as a function of gate bias, light intensity, and stress time. It has been found that, in case of electrical stress, the thrshold voltage shifts of a-Si:H TFT's may be attributed to the defect creation process at the early stage, while the charge trapping phenomena may be dominant when the stressing periods exceed about 2 hours. It has been also observed that the degradation in the device characteristics of a-Si:H TFT's is accelerated due to multiple stress effects, where the defect creation mechanism may be more responsible for the degradation rather than the charge trapping mechanism.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.37-43
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• 2008

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program/erase (P/E) speed, reliability of memory device on interface trap between Si substrate and tunneling oxide and bulk trap in nitride layer were investigated using charge pumping method which has advantage of simple and versatile technique. We analyzed different SANOS memory devices that were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SANOS cell transistors with larger capture cross section and interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. The data retention was deteriorated as increasing P/E cycling number but not coincides with interface trap increasing tendency. This result once again confirmed that interface trap independence on data retention. And the result on different program method shows that HCI program method more degraded by locally trapping. So, we know as a result of experiment that analysis the SANOS Flash memory characteristic using charge pumping method reflect the device performance related to interface and bulk trap.

• Transactions on Electrical and Electronic Materials
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• v.7 no.5
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• pp.235-239
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• 2006

Charge dynamics in polymeric materials after aged under ac electric field using the pulsed electroacoustic (PEA) technique is reported. The emphasis is placed on charge decay. The charge dynamics of the ac aged additive free low density polyethylene (LDPE) samples under dc bias differ from the sample without ac ageing, indicating changes brought in by ac ageing. It is believed that a slow decay rate of charge in the ac aged sample is related to the formation of deep traps in the material. However, chemical analysis by infrared spectroscope (FTIR) and Raman microscope reveals no significant chemical changes taken place in the bulk of the material after ac ageing. Further experiments on irradiated LDPE have revealed a similar behaviour, i.e. the charge decay is slower in irradiated samples than that of fresh sample. The findings presented clearly indicate that space charge measurement can be used as a diagnostic tool to monitor ageing in polymeric materials.