• 터널과지하공간
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• 제7권3호
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• pp.238-245
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• 1997

A transient pulse methos has been used to measure the permeability of Pocheon granite pre-heated from $25^{\circ}C$ to $600^{\circ}C$ at effective pressure up to 32MPa. The permeability of whole rock ranged from 0.72 $\mu$d at 10MPa to 0.20 $\mu$d at 32MPa. The permeability of rock heated to $600^{\circ}C$ ranged from 18.07$\mu$d at 10MPa to 6.39$\mu$d at 32MPa. Confining pressure has greater effects on the rocks thermally treated to lower thermal-cycle temperatures than on the higher thermally treated rocks. The increase of permeability is most pronounced between 40$0^{\circ}C$ and $600^{\circ}C$. Below 40$0^{\circ}C$, permeability increase is expected to be associated with the formation of new cracks and widening of preexisting cracks, whereas above 40$0^{\circ}C$, permeability increase is expected to reflect widening of cracks. Using the equivalent channel model, author shows that the exponent n in the relationship relating the permebility(k) to porosity($\phi$) by k∝$$\phi$^n$ falls in the range 2.7$\leq$n$\leq$3.0.

• 설비공학논문집
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• 제10권1호
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• pp.11-21
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• 1998

A numerical study is made on the ice-formation for water flow inside a stenotic tube. The study takes into account the interaction existing between the laminar flow and the stenotic port in the circular tube. In the solution strategy, the present study is substantially distinguished from the existing works In that the complete set of governing equations in both the solid and liquid regions are resolved. In a channel flow between parallel plates, the agreement of predictions and available experimental data is very good. Numerical results are mainly obtained by varying the height and length of a stenotic shape and additionally for several temperatures of the wall and inlet of tube. The results show that the shape of stenotic port has the great effect on the thickness of the solidification layer in the tube. As the height of a stenosis grows and the length of a stenosis decreases, the ice layer thickness near the stenotic port is thinner due to backward flow caused by the sudden expansion of water tunnel. It is also found that the ice layer becomes more fat In accordance with Reynolds number and the temperature of the wall and inlet of tube decreased.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.54-57
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• 2002

In this study, a new programming method, to minimize the generation of Si-SiO$_2$ interface traps of scaled SONOS flash memory as a function of number of program/erase cycles has been proposed. In the proposed programming method, power supply voltage is applied to the gate, forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim (MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and drain are open. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ prograss/erase cycles can be realized by the proposed programming method. The asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics of scaled SONOS devices because electrical stress applied to the Si-SiO$_2$ interface is reduced by short programming time.

• 한국전기전자재료학회논문지
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• 제16권1호
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• pp.5-10
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• 2003

In this study, a new programming method to minimize the generation of Si-SiO$_2$interface traps of SONOS nonvolatile memory device as a function of number of porgram/erase cycles was proposed. In the proposed programming method, power supply voltage is applied to the gate. forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim(MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and dram are left open. Also, the asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics or SONOS devices because electrical stress applied to the Si-SiO$_2$interface is reduced due to short program time.

• 한국전기전자재료학회논문지
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• 제13권10호
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• pp.822-827
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• 2000

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor field effect transistor) NVSM (nonvolatile semiconductor memory) cell is investigated by single junction charge pumping method. The device was fabricated by 0.35㎛ standard logic fabrication process including the ONO stack dielectrics. The thickness of ONO dielectricis are 24$\AA$ for tunnel oxide, 74 $\AA$ for nitride and 25 $\AA$ for blocking oxide, respectively. By the use of single junction charge pumping method, the lateral profiles of both interface and memory traps can be calculated directly from experimental charge pumping results without complex numerical simulation. The interface traps were almost uniformly distributed over the whole channel region and its maximum value was 7.97$\times$10$\^$10/㎠. The memory traps were uniformly distributed in the nitride layer and its maximum value was 1.04$\times$10$\^$19/㎤. The degradation characteristics of SONOSFET with write/erase cycling also were investigated.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.751-754
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• 2000

When charge-trap SONOS cells are used flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM cells were fabricated using 0.35$\mu\textrm{m}$ standard memory cell embedded logic process including the ONO cell process. based on retrograde twin-well, single-poly, single metal CMOS process. The thickness of ONO triple-dielectric for memory cell is tunnel oxide of 24${\AA}$, nitride of 74 ${\AA}$, blocking oxide of 25 ${\AA}$, respectively. The program mode(Vg: 7,8,9 V, Vs/Vd: -3 V, Vb: floating) and the erase mode(Vg: -4,-5,-6 V, Vs/Vd: floating, Vb: 3V) by modified Fowler-Nordheim(MFN) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation($\Delta$Vth, S, Gm) characteristics than channel MFN tunneling operation. Also the program inhibit conditions of unselected cell for separated source lines NOR-tyupe flash memory application were investigated. we demonstrated that the program disturb phenomenon did not occur at source/drain voltage of 1 V∼4 V and gate voltage of 0 V∼4.

• 진공이야기
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• 제3권3호
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• pp.15-18
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• 2016

In future wearable electronic systems, 3-dimensional (3D) devices have attracted much attention due to their high density integration and low-power functionality. Among 3D devices, gate-all-around (GAA) nanowire transistor provides superior gate controllability, resulting in suppressing short channel effect and other drawbacks in 2D metal-oxide-semiconductor field-effect transistor (MOSFET). Silicon nanowires (SiNWs) are the most promising building block for GAA structure device due to their compatibility with the current Si-based ultra large scale integration (ULSI) technology. Moreover, the theoretical limit for subthreshold swing (SS) of MOSFET is 60 mV/dec at room temperature, which causes the increase in Ioff current. To overcome theoretical limit for the SS, it is crucial that research into new types of device concepts should be performed. In our present studies, we have experimentally demonstrated feedback FET (FBFET) and tunnel FET (TFET) with sub-60 mV/dec based on SiNWs. Also, we fabricated SiNW based complementary TFET (c-TFET) and SiNW complementary metal-oxide-semiconductor (CMOS) inverter. Our research demonstrates the promising potential of SiNW electronic devices for future wearable electronic systems.

• 대한기계학회논문집
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• 제13권5호
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• pp.991-998
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• 1989

본 연구에서는 충돌각을 변수로 한 실험적 연구를 수행하기 위하여 여타의 변수를 고정하였으며, 유속은 R$_{e}$=5.2*$10^{4}$의 결과를 제시하였다.

• 터널과지하공간
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• 제32권6호
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• pp.451-463
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• 2022

수직갱도에서 붕괴사고가 일어났을 때, 붕괴현장의 위험도를 신속하게 평가하는 것은 매우 중요하다. 사고현장에서 추가적인 붕괴 위험 때문에 인력을 투입한 직접적인 조사는 불가능하다. 수백 미터 심도를 갖는 수직갱도에서는 무선 신호의 한계와 와류 때문에 고속 라이다 센서를 장착한 드론을 이용한 조사가 불가능하다. 기존 연구에서는 견인방식을 이용한 단일채널 Lidar 센서를 3차원 형상화 장비가 구현되어 적용되었다. 관성(IMU)센서 데이터를 바탕으로 탐사시 발생하는 회전 운동과 진자운동에 대한 보정이 이루어졌고, 인접 측정데이터 간의 유사성 검토를 통해 정밀 보정을 수행하였으나 탐사 깊이가 깊어질수록 오차가 누적되는 현상이 발견되었다(Kim et al.(2020)). 본 논문에서는 다중채널 Lidar 센서를 적용하여 견인장치에 의해 상승이동하면서 연속적인 단면데이터가 수집되었다. 다중채널 Lidar의 방사 특성 때문에 발생하는 데이터 중첩성을 이용하여 동일 심도의 측정데이터 간의 유사성을 통해 회전운동을 정밀 보정하기 위한 기법이 적용되었다. 180 m 심도의 수직갱도에서 구현된 탐사장비를 이용하여 0~165 m 구간이 조사하여 수직갱도의 형상이 3차원 그래픽으로 재구성되었다.

• 한국건축시공학회지
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• 제20권3호
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• pp.279-287
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• 2020

최근 지하형 탄약고에 대한 수요가 발생하고 사업이 구체화되고 있는 상황에서 지하형 탄약고에 대한 설계 방법의 부재가 상당한 걸림돌이 되고 있다. 본 연구에서 분석한 바와 같이 군 작전적 측면과 안전거리 기준 등의 안전 문제로 인해 민간에서 사용하는 일반적인 터널 설계 기준이나 지하형 탄약고에 대한 기존 연구결과들을 통해서는 제대로 된 지하형 탄약고를 구축할 수 없다. 따라서 실무자들이 지속적으로 순환되는 우리나라 군 및 관 특성상 표준화된 설계방법이 존재하지 않을 경우 지하형 탄약고의 설치는 상당히 지연될 수 밖에 없을 것이다. 이에 본 연구에서는 격실 설계, 격실 배치, 터널 및 출입구 설계, 공조설비 설계방법에 대해 고려해야할 사항들을 분석하고 전체적인 설계 프로세스를 정립하였다. 이를 토대로 설계 예시를 제공하였으며, 관련 전문가가 아니더라도 단계별로 설계를 따라 할 수 있도록 하였다. 지하형 탄약고는 세계적으로 시공사례가 많지 않다. 하지만 민·군 상생에 대한 국가 정책과 시장 추세를 비추어볼 때 지하형 탄약고에 대한 수요는 지속적으로 증가할 것으로 전망된다. 따라서 본 연구를 시작으로 지하형 탄약고에 대한 연구가 활성화되어 향후 대한민국이 기술 수출 등을 통해 세계 시장을 좌우할 수 있게 되기를 기대한다.