• Title/Summary/Keyword: Channel Charge

Search Result 282, Processing Time 0.031 seconds

Product-Resolved Photodissociations of Iodotoluene Radical Cations

  • Shin, Seung-Koo;Kim, Byung-Joo;Jarek, Russell L.;Han, Seung-Jin
    • Bulletin of the Korean Chemical Society
    • /
    • v.23 no.2
    • /
    • pp.267-270
    • /
    • 2002
  • Photodissociations of o-, m-, and p-iodotoluene radical cations were investigated by using Fourier-transform ion cyclotron resonance (FT-ICR) spectrometry. Iodotoluene radical cations were prepared in an ICR cell by a photoionization charge-transfer method. The time-resolved one-photon dissociation spectra were obtained at 532 nm and the identities of $C_7H_7^+$ products were determined by examining their bimolecular reactivities toward toluene-$d_8$. The two-photon dissociation spectra were also recorded in the wavelength range 615-670 nm. The laser power dependence, the temporal variation, and the identities of $C_7H_7^+$ were examined at 640 nm. The mechanism of unimolecular dissociation of iodotoluene radical cations is elucidated: the lowest barrier rearrangement channel leads exclusively to the formation of the benzyl cation, whereas the direct C-I cleavage channel yields the tolyl cations that rearrange to both benzyl and tropylium cations with dissimilar branching ratios among o-, m-, and p-isomers. With a two-photon energy of 3.87 eV at 640 nm, the direct C-I cleavage channel results in the product branching ratio, [tropylium cation]/[benzyl cation], in descending order, 0.16 for meta >0.09 for ortho >0.05 for para.

Variation of electrical properties in solution processed SiInZnO thin film transistors (용액공정을 이용하여 제작된 SiInZnO 박막 트랜지스터의 전기적 특성 변화)

  • Park, Ki-Ho;Choi, Jun-Young;Chun, Yoon-Soo;Ju, Byeong-Kwon;Lee, Sang-Yeol
    • Proceedings of the KIEE Conference
    • /
    • 2011.07a
    • /
    • pp.1453-1454
    • /
    • 2011
  • We have investigated the effect of silicon contents (0~0.4 molar ratios) on the performance of solution processed silicon-indium-zinc oxide (SIZO) thin-film transistors (TFTs). Despites its solution processed channel layer, low annealed temperature below $200^{\circ}C$ in air has been used for SIZO-TFTs. The $V_{th}$ is shifted from -4.04 to 5.15 V as increasing Si ratio in the SIZO-TFTs. The positive shift of $V_{th}$ as increasing Si contents in SIZO system indicates that Si suppresses the carrier generation in the active channel layer since $V_{th}$ is defined as the voltage required accumulating sufficient charge carriers to form a conductive channel path.

  • PDF

The fabrication process and optimum design of RESURF EDMOSFETs for smart power IC applications (Smart power IC용 RESURF EDMOSFETs의 제조공정과 최적설계)

  • 정훈호;권오경
    • Journal of the Korean Institute of Telematics and Electronics A
    • /
    • v.33A no.7
    • /
    • pp.176-184
    • /
    • 1996
  • To overcome the drawbacks of conventional LDMOSFETs, we propose RESURF EDMOSFETs which can be adapted in varous circuit applications, be driven without charge pumping circuity and thowe threshold voltage can be adjusted. The devices have the diffused drift region formed by a high tmperature process before the gate oxidaton. After the polysilicon gate electrode formation, a fraction of the drift region around the gate edge is opened for supplemental self-aligned ion implantation to obtain self-aligned drift region. This leads to a shorter gate length and desirable drift region junction contour under the gate edge for minimum specific-on-resistance. In additon, a and maximize the breakdown voltage. Also, by biasing the metal field plate, we can reduce the specific-on-resistance further. The devices are optimized by using the TSUPREM-4 process simulator and the MEDICI device simulator. The optimized devices have the breakdwon voltage and the specific-on-resistance of 101.5V and 1.14m${\Omega}{\cdot}cm^{2}$, respectively for n-channel RESURF EDMOSFET, and 98V and 2.75m.ohm..cm$^{2}$ respectively for p-channel RESURF EDMOSFET. To check the validity of the simulations, we fabricated n-channel EDMOSFETs and confirmed the measured breakdown voltage of 97V and the specific-on-resistance of 1.28m${\Omega}{\cdot}cm^{2}$. These results are superior to those of any other reported power devices for smart power IC applications.

  • PDF

Analysis of Subthreshold Swings Based on Scaling Theory for Double Gate MOSFET (이중게이트 MOSFET의 스켈링 이론에 대한 문턱전압이하 스윙분석)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.16 no.10
    • /
    • pp.2267-2272
    • /
    • 2012
  • This study has presented the analysis of subthreshold swings based on scaling theory for double gate MOSFET. To solve the analytical potential distribution of Poisson's equation, we use Gaussian function to charge distribution. The scaling theory has been used to analyze short channel effect such as subthreshold swing degradation. These scaling factors for gate length, oxide thickness and channel thickness has been modified with the general scaling theory to include effects of double gates. We know subthreshold swing degradation is rapidly reduced when scaling factor of gate length is half of general scaling factor, and parameters such as projected range and standard projected deviation have greatly influenced on subthreshold swings.

Fast High-throughput Screening of the H1N1 Virus by Parallel Detection with Multi-channel Microchip Electrophoresis

  • Zhang, Peng;Park, Guenyoung;Kang, Seong Ho
    • Bulletin of the Korean Chemical Society
    • /
    • v.35 no.4
    • /
    • pp.1082-1086
    • /
    • 2014
  • A multi-channel microchip electrophoresis (MCME) method with parallel laser-induced fluorescence (LIF) detection was developed for rapid screening of H1N1 virus. The hemagglutinin (HA) and nucleocapsid protein (NP) gene of H1N1 virus were amplified using polymerase chain reaction (PCR). The amplified PCR products of the H1N1 virus DNA (HA, 116 bp and NP, 195 bp) were simultaneously detected within 25 s in three parallel channels using an expanded laser beam and a charge-coupled device camera. The parallel separations were demonstrated using a sieving gel matrix of 0.3% poly(ethylene oxide) ($M_r$ = 8,000,000) in $1{\times}$ TBE buffer (pH 8.4) with a programmed step electric field strength (PSEFS). The method was ~20 times faster than conventional slab gel electrophoresis, without any loss of resolving power or reproducibility. The proposed MCME/PSEFS assay technique provides a simple and accurate method for fast high-throughput screening of infectious virus DNA molecules under 400 bp.

Highly Integrated 3-dimensional NOR Flash Array with Vertical 4-bit SONOS (V4SONOS) (수직형 4-비트 SONOS를 이용한 고집적화된 3차원 NOR 플래시 메모리)

  • Kim, Yoon;Yun, Jang-Gn;Cho, Seong-Jae;Park, Byung-Gook
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.47 no.2
    • /
    • pp.1-6
    • /
    • 2010
  • We proposed a highly integrated 3-dimensional NOR Flash memory array by using vertical 4-bit SONOS NOR flash memory. This structure has a vertical channel, so it is possible to have a long enough channel without extra cell area. Therefore, we can avoid second-bit effect, short channel effect, and redistribution of injected charges. And the proposed array structure is based on three-dimensional integration. Thus, we can obtain a NOR flash memory having $1.5F^2$/bit cell size.

A Subthreshold Slope and Low-frequency Noise Characteristics in Charge Trap Flash Memories with Gate-All-Around and Planar Structure

  • Lee, Myoung-Sun;Joe, Sung-Min;Yun, Jang-Gn;Shin, Hyung-Cheol;Park, Byung-Gook;Park, Sang-Sik;Lee, Jong-Ho
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.12 no.3
    • /
    • pp.360-369
    • /
    • 2012
  • The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.

Analysis for Breakdown Voltage of Double Gate MOSFET according to Device Parameters (소자파라미터에 따른 DGMOSFET의 항복전압분석)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.17 no.2
    • /
    • pp.372-377
    • /
    • 2013
  • This paper have presented the breakdown voltage for double gate(DG) MOSFET. The analytical solution of Poisson's equation and Fulop's breakdown condition have been used to analyze for breakdown voltage. The double gate(DG) MOSFET has the advantage to reduce the short channel effects as improving the current controllability of gate. But we need the study for the breakdown voltage of DGMOSFET since the decrease of the breakdown voltage is unavoidable. To approximate with experimental values, we have used the Gaussian function as charge distribution for Poisson's equation, and the change of breakdown voltage has been observed for device geometry. Since this potential model has been verified in the previous papers, we have used this model to analyze the breakdown voltage. As a result to observe the breakdown voltage, the smaller channel length and the higher doping concentration become, the smaller the breakdown voltage becomes. Also we have observed the change of the breakdown voltage for gate oxide thickness and channel thickness.

Relation of Threshold Voltage and Scaling Theory for Double Gate MOSFET (DGMOSFET의 문턱전압과 스켈링 이론의 관계)

  • Jung, Hak-Kee
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.16 no.5
    • /
    • pp.982-988
    • /
    • 2012
  • This paper has presented the relation of scaling theory and threshold voltage of double gate(DG) MOSFET. In the case of conventional MOSFET, current and switching frequency have been analyzed based on scaling theory. To observe the possibility of application of scaling theory for threshold voltage of DGMOSFET, the change of threshold voltage has been observed and analyzed according to scaling theory. The analytical potential distribution of Poisson equation has been used, and this model has been already verified. To solve Poisson equation, charge distribution such as Gaussian function has been used. As a result, it has been observed that threshold voltage is grealty changed according to scaling factor and change rate of threshold voltages is traced for scaling of doping concentration in channel. This paper has explained for the best modified scaling theory reflected the influence of two gates as using weighting factor when scaling theory has been applied for channel length and channel thickness.

Channel Selection Method of Wireless Sensor Network Nodes for avoiding Interference in 2.4Ghz ISM(Industrial, Scientific, Medical) Band (2.4Ghz ISM(Industrial Scientific Medical) 밴드에서 간섭을 회피하기 위한 무선 센서 노드의 채널 선택 방법)

  • Kim, Su Min;Kuem, Dong Hyun;Kim, Kyung Hoon;Oh, Il;Choi, Seung Won
    • Journal of Korea Society of Digital Industry and Information Management
    • /
    • v.10 no.4
    • /
    • pp.109-116
    • /
    • 2014
  • In recent, ISM (Industrial Scientific Medical) band that is 2.4GHz band authorized free of charge is being widely used for smart phone, notebook computer, printer and portable multimedia devices. Accordingly, studies have been continuously conducted on the possibility of coexistence among nodes using ISM band. In particular, the interference of IEEE 802.11b based Wi-Fi device using overlapping channel during communication among IEEE 802.15.4 based wireless sensor nodes suitable for low-power, low-speed communication using ISM band causes serious network performance deterioration of wireless sensor networks. This paper examined a method of identifying channel status to avoid interference among wireless communication devices using IEEE 802.11b (Wi-Fi) and other ISM bands during communication among IEEE 802.15.4 based wireless sensor network nodes in ISM band. To identify channels occupied by Wi-Fi traffic, various studies are being conducted that use the RSSI (Received Signal Strength Indicator) value of interference signal obtained through ED (Energy Detection) feature that is one of IEEE 802.15.4 transmitter characteristics. This paper examines an algorithm that identifies the possibility of using more accurate channel by mixing utilization of interference signal and RSSI mean value of interference signal by wireless sensor network nodes. In addition, it verifies such algorithm by using OPNET Network verification simulator.