• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.29-35
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• 1998

This paper describes architectures and design of a SIMD type parallel image processing chip called SliM-II. The chiphas a linear array of 64 processing elements (PEs), operates at 30 MHz in the worst case simulation and gives at least 1.92 GIPS. In contrast to existing array processors, such as IMAP, MGAP-2, VIP, etc., each PE has a multiplier that is quite effective for convolution, template matching, etc. The instruction set can execute an ALU operation, data I/O, and inter-PE communication simulataneously in a single instruction cycle. In addition, during the ALU/multiplier operation, SliM-II provides parallel move between the register file and on-chip memory as in DSP chips, SliM-II can greatly reduce the inter-PE communication overhead, due to the idea a sliding, which is a technique of overlapping inter-PE communication with computation. Moreover, the bandwidth of data I/O and inter-PE communication increases due to bit-parallel data paths. We used the COMPASS$^{TM}$ 3.3 V 0.6.$\mu$m standrd cell library (v8r4.10). The total number of transistors is about 1.5 muillions, the core size is 13.2 * 13.0 mm$^{2}$ and the package type is 208 pin PQ2 (Power Quad 2). The performance evaluation shows that, compared to a existing array processors, a proposed architeture gives a significant improvement for algorithms requiring multiplications.s.

• Journal of fish pathology
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• v.27 no.2
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• pp.99-105
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• 2014

Biosensors consist of biochemical recognition agents like antibodies immobilized on the surfaces of transducers that change the recognition into a measurable electronic signal. Here we report a piezoelectric immunosensor made to detect Vibrio vulnificus. A 9MHz AT-cut piezoelectric wafer attached with two gold electrodes of 5mm diameter was used as the transducer of the QCM biosensor with a reproducibility of ${\pm}0.1Hz$ in frequency response. We have tried different approaches to immobilize antibody on the sensor chip. Concerning the orientation of antibody for the best antigen binding capacity, the antibody was immobilized by specific binding to protein G or by cross-linking through hydrazine. In addition, protein G was cross-linked on glutaraldehyde activated immine layer (PEI) or EDC/NHS activated sulfide monolayer (MPA). PEI was found to be more effective to immobilize protein G following glutaraldehyde activation than MPA. However, hydrazine chip showed a better capability to immobilize more IgG than protein G chip and a higher sensitivity. The sensor system was able to detect V. vulnificus in dose dependent manner and was able to detect bacterial cells within 5 minutes by monitoring frequency shifts in real time. The detection limit can be improved by preincubation to enrich the bacterial cell number.

• The Journal of Korean Obstetrics and Gynecology
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• v.20 no.3
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• pp.65-80
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• 2007

Purpose: This study is to examine anti-obesity effect and cytotoxicity of the long-term oral administration of Ephedra Sinica(Ma-hwang, ES) Methods: Using diet-induced obesity C57BL/6 mouse model, anti-obesity effect and DNA chip expression and cytotoxicity of the long-term oral administration of this herbal extract were investigated. Results: The herbal extract treated groups were arrested in weight increment only when they were lodged together. Such effects were abolished when they kept individually. ES fed mice behaved very rudely and violently. On the basis of histological studies of liver tissues and also in vitro cytotoxicity tests of the liver and kidney cell lines, no significant toxicity was found by 14 weeks of ES treatments. However, we found significant changes in gene expression profile in ES treated group by micro-array analysis. In case of ES group, up-regulated genes were 113 and down-regulated were 120. Some of lipid metabolism related genes also significantly changed in treatment groups. Conclusion: ES had effects of increasing the basal metabolic rate by stimulating the sympathetic nervous systems.

• Proceedings of the Korean Society for Bioinformatics Conference
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• 2006.02a
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• pp.83-89
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• 2006

Cellular functions are carried out by a concerted action of biochemical pathways whose components have genetic interactions. Abnormalities in the activity of the genes that constitute or modulate these pathways frequently have oncogenic implications. Therefore, identifying the upstream regulatory genes for major biochemical pathways and defining their roles in carcinogenesis can have important consequences in establishing an effective target-oriented antitumor strategy We have analyzed the gene expression profiles of human liver cancer samples using cDNA microarray chips enriched in liver and/or stomach-expressed cDNA elements, and identified groups of genes that can tell tumors from non-tumors or normal liver, or classify tumors according to clinical parameters such as tumor grade, age, and inflammation grade. We also set up a high-throughput cell-based assay system (cell chip) that can monitor the activity of major biochemical pathways through a reporter assay. Then, we applied the cell chip platform for the analysis of the HCC-associated genes discovered from transcriptome profiling, and found a number of cancer marker genes having a potential of modulating the activity of cancer-related biochemical pathways such as E2F, TCF, p53, Stat, Smad, AP-1, c-Myc, HIF and NF-kB. Some of these marker genes were previously blown to modulate these pathways, while most of the others not. Upon a fast-track phenotype analysis, a subset of the genes showed increased colony forming abilities in soft agar and altered cell morphology or adherence characteristics in the presence of purified matrix proteins. We are currently analyzing these selected marker genes in more detail for their effects on various biological Processes and for Possible clinical roles in liver cancer development.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.221-225
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• 2000

We designed asynchronous event logic library with 0.25$\mu\textrm{m}$ CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6㎓. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about 1.1mm ${\times}$ 1.1mm.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1098-1100
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• 2005

The floorplanning problem is an essential design step in VLSI layout design and it is how to place rectangular modules as density as possible. And then, as the DSM advances, the VLSI chip becomes more congested even though more metal layers are used for routing. Usually, a VLSI chip includes several buses. As design increases in complexity, bus routing becomes a heavy task. To ease bus routing and avoid unnecessary iterations in physical design, we need to consider bus planning in early floorplanning stage. In this paper, we propose a floorplanning method for topological constraint consisting of bus constraint and memory constraint. The proposed algorithms based on Genetic Algorithm(GA) is adopted a sequence pair. For selection control, new objective functions are introduced for topological constraint. Studies on floor planning and cell placement have been reported as being applications of GA to the LSI layout problem. However, no studies have ever seen the effect of applying GA in consideration of topological constraint. Experimental results show improvement of bus and memory constraint.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.155-164
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• 1996

The architecture of a programmable video codec IC is described that employs multiple vector processors in a single chip. The vector processors operate in parallel and communicate with one another through on-chip shared memories. A single scalar control processor schedules each vector processor independently to achieve real-tiem video coding with special vector instructions. With programmable interconnection buses, the proposed architecture performs multi-processing of tasks and data in video coding. Therefore, it can provide good parallelism as well as good programmability. especially, it can operate multithread video coding, which processes several independent image sequences simultaneously. We explain its scheduling, multithred video coding, and vector processor architectures. We implemented a prototype video codec with a 0.8um CMOS cell-based technology for the multi-standard videophone. This codec can execute video encoding and decoding simultaneously for the QCIF image at a frame rate of 30Hz.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.22-38
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• 1997

This paper proposes a new VLSI architecture for morphological filters and presents its chip design and implementation. The proposed architecture can significantly reduce hardware costs compared with existing architecture by using a feedback loop path to reuse partial results and a decoder/encoder pair to detect maximum/minimum values. In addition, the proposed architecture requires one common architecture for both diltion and erosion and fewer number of operations. Moreover, it can be easily extended for larger size morphologica operations. We developed VHDL (VHSIC hardware description language) models, performed logic synthesis using the SYNOPSYS CAD tool. We used the SOG (sea-of-gate) cell library and implemented the actual chip. The total number of gates is only 2,667 and the clock frequency is 30 MHz that meets real-time image processing requirements.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4C
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• pp.388-397
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• 2002

We designed a SIMD-DSP/FPU that can efficiently improve multimedia processing performance when integrated into high-performance embedded microprocessors. We proposed partitioned architectures and new schemes for several functional units to reduce chip area. Sharing functional units reduces the area of FPU significantly. The proposed architecture is modeled in HDL and synthesized with a 0.35$\mu\textrm{m}$ standard cell library. The chip area is estimated to be about 100,000 equivalent gates. The designed unit can run at higher than 50MHz clock frequency of CPU core under the worst-case operating conditions.

• Proceedings of the KSME Conference
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• 2008.11b
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• pp.2696-2699
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• 2008

Microfluidic chips have been frequently utilized to perform biochemical analysis, like cell culture, because they reduce the consumptions of analytes and reagents and automate multi-step analysis processes. It is often critical to monitor temperature in a microchannel for the analyses in order to control a reaction condition of bio or chemical molecules. We propose a novel method to monitor temperature of a microchannel flow by using polydiacetylene (PDA), a conjugated polymer, that has a unique property to transform its color from visible blue to fluorescent red by thermal stress. We inject PDA sensor droplets generated by hydrodynamic instability into a microchannel with a microheater incorporated on the channel bottom. Also, we change the channel temperature by providing the different electric power to the microheater. The results show that the florescence intensity of PDA sensor droplets linearly increases in response to the flow temperature increase within a certain range.