• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.289-440
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• 1998

This paper describes an interconnection network structure which transports information among processors through a high speed ATM switch. To efficiently use the high speed ATM switch for the message-based multiprocessor, we implemented the cell router that performs multiplexing and demultiplexing of cells from/to processors. In this system, we use the expanded internal cell format including 3bytes for switch routing information. This interconnection network has 3 stage routing strategies: ATM switch routing using switch routing information, cell router routing using a virtual path identifier (VPI) and cell reassembly routing using a virtual channel indentifier (VCI). The interconnection network consists of the NxN folded switch and N cell routers with the M processor interface. Therefore, the maximum number of NxM processors can be interconnected for message communication. This interconnection network using the ATM switch makes a significant improvement in terms of message passing latency and scalability. Additionally, we evaluated the transmission overhead in this interconnection network using ATM switch.

• 신재생에너지
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• 제16권3호
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• pp.1-12
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• 2020

Shingled technology is the latest cell interconnection technology developed in the photovoltaic (PV) industry due to its reduced resistance loss, low-cost, and innovative electrically conductive adhesive (ECA). There are several advantages associated with shingled technology to develop cell to module (CTM) such as the module area enlargement, low processing temperature, and interconnection; these advantages further improves the energy yield capacity. This review paper provides valuable insight into CTM loss when cells are interconnected by shingled technology to form modules. The fill factor (FF) had improved, further reducing electrical power loss compared to the conventional module interconnection technology. The commercial PV module technology was mainly focused on different performance parameters; the module maximum power point (Pmpp), and module efficiency. The module was then subjected to anti-reflection (AR) coating and encapsulant material to absorb infrared (IR) and ultraviolet (UV) light, which can increase the overall efficiency of the shingled module by up to 24.4%. Module fabrication by shingled interconnection technology uses EGaIn paste; this enables further increases in output power under standard test conditions. Previous research has demonstrated that a total module output power of approximately 400 Wp may be achieved using shingled technology and CTM loss may be reduced to 0.03%, alongside the low cost of fabrication.

• 한국태양에너지학회:학술대회논문집
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• 한국태양에너지학회 2008년도 춘계학술발표대회 논문집
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• pp.241-246
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• 2008

In this paper, we analyze the I-V curve and hot-spot phenomenon caused by solar cells' serial and parallel connected circuit. The mis-match loss of parallel interconnection with low Isc string decrease lower than serially interconnected one and temperature caused by hot-spot does. Also, mis-match loss of parallel interconnection with low Voc string increase more than serially interconnected one. The string having low Voc happened hot-spot phenomenon when open circuit. The bad solar cell in string gives revere bias to good solar cell and make hot-spot phenomenon. If we consider the mis-match loss, when designing PV module and array. the efficiency of PV system might increase.

• 전자공학회논문지A
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• 제33A권7호
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• pp.143-148
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• 1996

Detailed analyses have been presentd for a basic single-electron-logic-cell consisting of two single-electron-transistors (SETs) in series. The interconnection between two SETs has been treated as a coulomb island and the joint probability density function of all three coulomb islands (two from the SETs and one form the interconnection) has been exactly calculated. The average number of electrons in each coulomb island and the steady-state ouptut voltage have been calculated and analyzed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.216-217
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• 2007

In this study, we analyzed the electrical loss characteristics between ribbon and output terminal of constituent material according to electrical resistance during interconnection process of PV module. From this result, the electrical output power reduction rate caused by interaction between ribbon and cell's interconnection was 2.88%. There was 1W electrical output power reduction through the 16 solar cells. So it is expected that the wider size of PV module gives the higher loss in electricity production. Also, the average output power of PV module passed lamination process was increased by 0.081W per one solar cell and the increase rate was 3.7%.PV module's electrical loss before and after lamination process according to constituent material's terminal was 0.49W and 0.50W, respectively.

• 반도체디스플레이기술학회지
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• 제10권2호
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• pp.73-81
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• 2011

We manufactured the inkjet printing system for the application into the nano Ag finger line interconnection process in Si solar cells. The home-made inkjet printer consists of motion part for XY motion stage with optical table, head part, power and control part in the rack box with pump, and ink supply part for the connection of pump-tube-sub ink tanknozzle. The ink jet printing system has been used to conduct the interconnection process of finger lines on Si solar cell. The nano ink includes the 50 nm-diameter. Ag nano particles and the viscosity is 14.4 cP at $22^{\circ}C$. After processing of inkjet printing on the finger lines of Si solar cell, the nano particles were measured by scanning electron microscope. After the heat treatment at $850^{\circ}C$, the finger lines showed the smooth surface morphology without micropores.

• 전자공학회지
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• 제24권6호
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• pp.38-49
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• 1997

0.4mm Resign Rule의 Super Low Power Dissipation, Low Voltage. Operation-5- Full CMOS SRAM Cell을 개발하였다. Retrograde Well과 PSL(Poly Spacer LOCOS) Isolation 공정을 사용하여 1.76mm의 n+/p+ Isolation을 구현하였으며 Ti/TiN Local Interconnection을 사용하여 Polycide수준의 Rs와 작은 Contact저항을 확보하였다. p-well내의 Boron이 Field oxide에 침적되어 n+/n-well Isolation이 취약해짐을 Simulation을 통해 확인할 수 있었으며, 기생 Lateral NPN Bipolar Transistor의 Latch Up 특성이 취약해 지는 n+/n-wellslze는 0.57mm이고, 기생 Vertical PNP Bipolar Transistor는 p+/p-well size 0.52mm까지 안정적인 Current Gain을 유지함을 알 수 있었다. Ti/TiN Local Interconnection의 Rs를 Polycide 수준으로 낮추는 것은 TiN deco시 Power를 증가시키고 Pressure를 감소시킴으로써 실현할 수 있었다. Static Noise Margin분석을 통해 Vcc 0.6V에서도 Cell의 동작 Margin이 있음을 확인할 수 있었으며, Load Device의 큰 전류로 Soft Error를 개선할수 있었다. 본 공정으로 제조한 1M Full CMOS SRAM에서 Low Vcc margin 1.0V, Stand-by current 1mA이하(Vcc=3.7V, 85℃기준) 를 얻을 수 있었다.

• 한국전기화학회:학술대회논문집
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• 한국전기화학회 2000년도 추계총회 및 학술발표회
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• pp.49-49
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• 2000

• Journal of Electrical Engineering and Technology
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• 제1권2호
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• pp.192-199
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• 2006

This paper presents an improved anti-islanding algorithm for utility interconnection of multiple distributed fuel cell powered generations (DFPGs). A cross-correlation method is proposed and implemented in conjunction with the anti-islanding algorithm developed in the previous work [I]. While the power control algorithm continuously perturbs $({\pm}5%)$ the reactive power supplied by the DFPG, the proposed algorithm calculates the cross-correlation index of a rate of change of the frequency deviation with respect to $({\pm}5%)$ the reactive power to confirm islanding. If this index is above 50%, the algorithm further initiates $({\pm}10%)$ the reactive power perturbation and continues to calculate the correlation index. If the index exceeds 80%, the occurrence of islanding can be confirmed. The proposed method is robust and capable of detecting the occurrence of islanding in the presence of several DFPGs, which are independently operating. Viability of the cross-correlation method is verified by the simulation. Experimental results are presented to support the findings of the proposed method.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 추계학술대회 논문집 학회본부
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• pp.569-571
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• 1995

This paper compares the simulated annealing and the Hopfield neural network method for an optimal routing in a multistage interconnection network(MIN). The MIN provides a multiple number of paths for ATM cells to avoid cell conflict. Exhaustive search always finds the optimal path, but with heavy computation. Although greedy method sets up a path quickly, the path found need not be optimal. The simulated annealing can find an sub optimal path in time comparable with the greedy method.