• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.270-277
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• 2012

This paper presents a new DAC design strategy to achieve a wideband dynamic linearity by increasing the bandwidth of the output impedance. In order to reduce the dominant parasitic capacitance of the conventional matrix structure, all the cells associated with a unit current source and its control are stacked in a single column very closely (stacked unit cell structure). To further reduce the parasitic capacitance, the size of the unit current source is considerably reduced at the sacrifice of matching yield. The degraded matching of the current sources is compensated for by a self-calibration. A prototype 6-bit 3.3-GS/s current-steering full binary DAC was fabricated in a 1P9M 90 nm CMOS process. The DAC shows an SFDR of 36.4 dB at 3.3 GS/s Nyquist input signal. The active area of the DAC occupies only $0.0546mm^2$ (0.21 mm ${\times}$ 0.26 mm).

• E2M - 전기 전자와 첨단 소재
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• 제7권1호
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• pp.7-14
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• 1994

Structural and optical characteristics in $SnO_2$/a-Se/Al sample by aging variation and applying constant voltage had been investigated. a-Se was varied with monoclinic structure and its surface was greatly exchanged. Its capacitance was first decreased and then increased and its photo-current, photo-voltage and photo-capacitance were increased gradually with day and applying voltage. From the results, crystallization of a-Se and dopant trap level formation had been identified. Also, it was acknowledged $SnO_2$/a-Se/Al sample is useful in photovoltaic and solid thin film cell.

• ETRI Journal
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• 제26권6호
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• pp.583-588
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• 2004

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of $3.63{\mu}m^2$. We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when $V_{cc}$ is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.

• 전기전자학회논문지
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• 제24권3호
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• pp.845-852
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• 2020

3 나노미터 아래의 미래공정에서는 작은 면적의 표준셀(Standard Cell)을 구현하는 데에 많은 기술적인 개선을 요구한다. 따라서 어떠한 기술을 통해 얼마나 작은 면적의 표준셀을 구현할 수 있는지, 그리고 그 영향이 어떠한지 알아보는 것은 매우 중요하다. 본 논문에서는 3 나노미터와 이하의 미래공정에서 표준셀 설계를 위해 묻힌 전력망(Buried Power Rail, BPR)과 상호보완 FET(Complementary FET, CFET)이 면적 감소에 얼마나 기여하는지 살펴보며 그 영향을 기생 캐패시턴스 관점에서 분석한다. 본 논문을 통해 상호보완 FET은 4T 이하의 표준셀을 구현할 수 있는 기술이지만, Z-축으로 증가하는 높이만큼 상당한(+18.0% 이상) 기생 Cap의 영향을 받는다는 점을 밝힌다.

• 대한기계학회논문집B
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• 제37권8호
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• pp.775-780
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• 2013

일반적으로 전기자동차(Electric Vehicle, EV)의 배터리로는 리튬-이온 전지가 많이 사용된다. 리튬-이온 전지는 충전이 가능한 이차 전지의 일종으로 마이크로 스케일의 극판과 분리막이 반복하여 적층된 구조를 가지고 있다. 이와 같은 미세구조로 인해 상세해석모형을 적용하는 것은 지나치게 많은 비용이 소모되는 일이다. 본 연구에서는 리튬-이온 전지를 하나의 등가물성으로 나타내는 방법을 제시하고 있으며, 185.3Ah 전지와 20Ah 전지에 이를 적용하여 그 결과를 이전자료와 비교하고 있다. 또한 집중용량법을 적용한 계산 결과를 함께 제시하여 유한요소법(FEM)이나 유한체적법(FVM)의 사용 없이 손쉽게 전지의 열적 거동을 확인할 수 있는 방법을 제시하였다.

• Journal of Power Electronics
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• 제12권1호
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• pp.40-48
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• 2012

This paper proposes the State-of-charge (SOC) estimator of a LiPB Battery using the Extended Kalman Filter (EKF). EKF can work properly only with an accurate model. Therefore, the high accuracy electrical battery model for EKF state is discussed in this paper, which is focused on high-capacity LiPB batteries. The battery model is extracted from a single cell of LiPB 40Ah, 3.7V. The dynamic behavior of single cell battery is modeled using a bulk capacitance, two series RC networks, and a series resistance. The bulk capacitance voltage represents the Open Circuit Voltage (OCV) of battery and other components represent the transient response of battery voltage. The experimental results show the strong relationship between OCV and SOC without any dependency on the current rates. Therefore, EKF is proposed to work by estimating OCV, and then is converted it to SOC. EKF is tested with the experimental data. To increase the estimation accuracy, EKF is improved with a single dominant varying parameter of bulk capacitance which follows the SOC value. Full region of SOC test is done to verify the effectiveness of EKF algorithm. The test results show the error of estimation can be reduced up to max 5%SOC.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 영호남학술대회 논문집
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• pp.124-127
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• 2000

The purpose of this study is to research and develop PAn-Carbon composite electrode for Supercapacitor. Supercapacitor cell of PAn-Carbon composite electrode with 1M $LiClO_{4}/IPC$ brings out good capacitor performance below 4.0V. The radius of semicircle of PAn-Carbon composite electrode adding 30wt% Acetylene Black was absolutely small. The total resistance of Supercapacitor cell mainly depended on internal resistance of he electrode. The discharge capacitance of PAn-Carbon on composite with 30wt% Acetylene Black in 1st and 50th cycles was 29 and 31F/g at current density of $1mA/cm^2$. The capacitance of PAn-Carbon composite with 30wt% Acetylene Black capacitor was larger than that of PAn capacitor without Acetylene Black. The coulombic efficiency of supercapacitor at discharge process of 1 and 50 cycles were 94 and 100%. respectively. PAn-Carbon composite Supercapacitor with 30wt.% Acetylene Black content showed good capacitance and stability with cycling.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2003년도 춘계전력전자학술대회 논문집(1)
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• pp.235-238
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• 2003

Photovoltaic(PV) array, which is generally installed outside, has the possibility to be damaged by high voltage due to lightning. Because the surge characteristics of PV array have not b eon fully Identified yet, there is a very important issue whether PV array should be connected with ground or not. In this paper, a basic model of PV array is provided considering the PV cell's barrier capacitance and ground capacitance for analysis of surge characteristics.

• Bulletin of the Korean Chemical Society
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• 제31권12호
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• pp.3852-3855
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• 2010

• 전력전자학회논문지
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• 제23권4호
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• pp.247-255
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• 2018

This paper proposes a transformer design of a direct cell-to-cell active cell balancing circuit with a multi-winding transformer for battery management system (BMS) applications. The coupling coefficient of the multi-winding transformer and the output capacitance of MOSFETs significantly affect the balancing current transfer efficiency of the cell balancing operation. During the operation, the multi-winding transformer stores the energy charged in a specific source cell and subsequently transfers this energy to the target cell. However, the leakage inductance of the multi-winding transformer and the output capacitance of the MOSFET induce an abnormal energy transfer to the non-target cells, thereby degrading the transfer efficiency of the balancing current in each cell balancing operation. The impacts of the balancing current transfer efficiency deterioration are analyzed and a transformer design methodology that considers the coupling coefficient is proposed to enhance the transfer efficiency of the balancing current. The efficiency improvements resulting from the selection of an appropriate coupling coefficient are verified by conducting a simulation and experiment with a 1 W prototype cell balancing circuit.