• Journal of Korea Multimedia Society
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• v.22 no.11
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• pp.1280-1287
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• 2019

For developing a wireless implantable device to monitoring the artery variation in real-time. The concept of a special vessel variation measurement capacitive sensor is presented in this paper. The sensor consists of two part; main sensor to measuring the arterial variation, and reference sensor is used to improve the accuracy of the capacitance value variation. Before sensor manufacture, a model of the sensor attached on the artery was designed in 3D to conduct in the FEA simulation to validate the validity and feasibility of the idea. The artery model was designed as layered structures and made of collagenous soft tissues with intima inside, followed by the media and the adventitia. Also, a grease layer was designed in the inner of the arterial wall to imitate the clogged arteries. The simulation was divided into two parts; sensor performance test by changing the diameter of the grease layer, and arterial wall tension test by changing the blood pressure. As the simulation results, the capacitance value measured by the proposed sensor is decreased follow the diameter of the grease increased. Also, large elastic deformation of the arterial wall since changing the blood pressure has been observed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.10-15
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• 2008

In this paper, a new NMOS gate cross-connected current-mirror type bridge rectifier for UHF RFID applications is presented. The DC converting characteristics of the proposed rectifier are analyzed with the high frequency equivalent circuit and the gate capacitance reduction technique for reducing the gate leakage current due to the increasing of operating frequency is also proposed theoretically by circuitry method. As the results, the proposed rectifier shows nearly same DC output voltages as the existing NMOS gate cross-connected rectifier, but it shows the gate leakage current reduced to less than 1/4 and the power consumption reduced more than 30% at the load resistor, and it shows more stable DC supply voltages for the valiance of load resistance. In addition, the proposed rectifier shows high enough and well-rectified DC voltages for the frequency range of 13.56MHz HF(for ISO 18000-3), 915MHz UHF(for ISO 18000-6), and 2.45 GHz microwave(for ISO 18000-4). Therefore, the proposed rectifier can be used as a general purpose one to drive RFID transponder chips on various RFID systems which use specified frequencies.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.8
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• pp.873-879
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• 2007

We have implemented a highly efficient 2.14-GHz class-F amplifier using Freescale 4-W peak envelope power(PEP) RF Si lateral diffusion metal-oxide-semiconductor field effect transistor(LDMOSFET). Because the control of the all harmonic contents is very difficult, we have managed only the $2^{nd}\;and\;3^{rd}$ harmonics to obtain the high efficiency with simple harmonic control circuit. In order to design the harmonic control circuit accurately, we extracted the bonding wire inductance and drain-source capacitance which are dominant parasitic and package effect components of the device. And then, we have fabricated the class-F amplifier. The measured drain and power-added efficiency are 65.1 % and 60,3 %, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.6
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• pp.590-598
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• 2004

An active capacitance circuit which employs series feedback network for the implement of negative resistance and low noise operation is analyzed in depth and its application to low noise active RF BPF's is discussed. Whereas many authors reported a lot of circuits that embody negative resistance circuit most of them have concerns for the equivalent resistance and reactance value at the center frequency. In this case, it could be possible to face a problem that the negative resistance circuit becomes unstable, or have poor flatness in passband because of insufficient forecast for the negative resistance values as the frequency goes higher or lower. In this paper, we extracted the exact equivalent values of this circuit and analyzed the RF characteristics with the varying the values of active devices and feedback circuits and presented the method that the flatness of passband can be improved. We have designed a 4-pole active BPF, which has the bandwidth of 60 ㎒, 0.67 ㏈ insertion loss, 0.3 ㏈ ripple, and noise figure of 3.0 ㏈ at 1.99 ㎓ band.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.2
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• pp.214-219
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• 2011

This paper presents a multi-band low noise amplifier(LNA) with switching operation for 2.4, 3.5 and 5.2 GHz bands using CMOS 0.18 um technology. The proposed circuit uses switching transistors to achieve the input and output matching for multi-band. By using the switching transistors, we can adjust the transconductance, gate inductance and gatesource capacitance at input stage and total output capacitance at output stage. The proposed LNA exhibits gain of 14.2, 12 and 11 dB and noise figure(NF) of 3, 2.9 and 2.8 dB for 2.4, 3.5 and 5.2 GHz, respectively.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.5
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• pp.185-190
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• 2002

Capacitor material utilized in the downsizing passive devices and dynamic random access memory(DRAM) requires the physical and electrical properties at given area such as capacitor thickness reduction, relative dielectric constant increase, low leakage current and thermal stability. Common capacitor materials, $SiO_2$, $Si_3N_4$, $SiO_2$/$Si_3N_4$,TaN and et al., used until recently have reached their physical limits in their application to several hundred angstrom scale capacitor. $Ta_2O_{5}$ is known to be a good alternative to the existing materials for the capacitor application because of its high dielectric constant (25 ~35), low leakage current and high breakdown strength. Despite the numerous investigations of $Ta_2O_{5}$ material, there have little been established the clear understanding of the annealing effect on capacitance characteristic and conduction mechanism, design and fabrication for $Ta_2O_{5}$ film capacitor. This study presents the structure-property relationship of reactive-sputtered $Ta_2O_{5}$ MIM capacitor structure processed by annealing in a vacuum. X-ray diffraction patterns skewed the existence of amorphous phase in as-deposited condition and the formation of preferentially oriented-$Ta_2O_{5}$ in 670, $700^{\circ}C$ annealing. On 670, $700^{\circ}C$ annealing under the vacuum, the leakage current decrease and the enhanced temperature-capacitance characteristic stability. and the leakage current behavior is stable irrespective of applied electric field. The results states that keeping $Ta_2O_{5}$ annealed at vacuum gives rise to improvement of electrical characteristics in the capacitor by reducing oxygen-vacancy and the broken bond between Ta and O.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.172-180
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• 2003

Based on simulation results and accompanying analysis, we suggest a thyristor-type ESD protection device structure suitable for implementation in standard CMOS processes to reduce the parasitic capacitances added to the input nodes, which is very important in CMOS RF ICs. We compare DC breakdown characteristics of the suggested device to those of a conventional NMOS protection device to show the benefits of using the suggested device for ESD protection. The characteristic improvements are demonstrated and the corresponding mechanisms are explained based on simulations. Structure dependencies are also examined to define the optimal structure. AC simulation results are introduced to estimate the magnitude of reduction in the added parasitic capacitance when using the suggested device for ESD protection. The analysis shows a possibility of reducing the added parasitic capacitance down to about 1/40 of that resulting with a conventional NMOS protection transistor, while maintaining robustness against ESD.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.11
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• pp.1543-1550
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• 2015

Ferroresonance is a non-linear vibrational phenomenon that is generated by the electrical interaction of the inductance component with the capacitor component of a certain capacitance as the device of the inductance component such as a transformer is saturated due to the degradation, the waveform distortion of current and voltage, and the oscillation of overcurrent and overvoltage in a system. Recently, ferroresonance was generated from the waveform distortion of current and voltage, or the overvoltage or undervoltage phenomenon caused by the nature of an electrical power system and design technology of the transformer in the three phase transformer system. Hence, in general, ferroresonance analyzed by converting to the LC equivalent circuit. However, in general, the aforementioned analytical method only applies to the resonance phenomenon that is generated by the interaction of the capacitance of bussbar and grounding, and switching as the capacitor component with PT and the transformer as the inductance component in a system. Subsequently, the condition where ferroresonance was generated since overvoltage was supplied as line voltage to the phase voltage and thus the iron core is saturated due to the interconnection between grounded and ungrounded systems could not be analyzed when single phase PT was connected in a ${\Delta}$/Y connection system. In this study, voltage swell in the configuration of grounded circuit of a step-up transformer with the ${\Delta}-{\Delta}$ connection linked to PT for control power and the ferroresonance generated by overvoltage when the line voltage of the ${\Delta}-{\Delta}$ connection was connected to the phase voltage of the grounded Y-Y connection were analyzed using PSCAD / EMTDC through the failure case of the transformer caused by ferroresonance in the system with the ${\Delta}-{\Delta}$/Y-Y connection, and subsequently, the preventive measure of ferroresonance was proposed.

• Tribology and Lubricants
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• v.40 no.4
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• pp.111-117
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• 2024

Due to global CO₂ emission reductions and fuel efficiency regulations, the trend toward transitioning from internal combustion engine vehicles to electric vehicles (EVs) has accelerated. Consequently, the problem of EV failures has become a focal point of active research. The parasitic capacitance generated during motor-shaft rotation induces voltage that deteriorates the raceway and ball surfaces of bearings, causing electrical damage in EVs. Despite numerous attempts to address this issue, most studies have been conducted under high viscosity lubricant and low load conditions. However, due to factors such as high-speed operation, rapid acceleration and deceleration, motor heating, and motor system-decelerator integration, current EV applications have shown diminished stability in lubrication films of motor bearings, thereby leveraging the investigation to address the risk of electrical damage. This study investigates the electrical damage to rolling bearing elements in EV motor drive systems. The experimental analysis focuses on the effects of electric currents and operational loads on bearing integrity. A test rig is designed to generate high-rate voltage specific to a motor system's parasitic capacitance, and bearing samples are exposed to these currents for specified durations. Component evaluation involves visual inspections and vibration measurements. In addition, a predictive model for electrical failure is developed based on accumulated data, which demonstrates the ability to predict the likelihood of electrical failure relative to the duration and intensity of current exposure. This in turn reduces uncertainties in practical applications regarding electrical erosion modes.

• Journal of IKEEE
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• v.22 no.4
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• pp.1025-1030
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• 2018

The proposed modulator is designed by utilizing a conventional structure employing time division technique to realize the 4th order delta-sigma modulator using one op-amp. In order to reduce the influence of KT/C noise, the capacitance in the first and second integrators reused was chosen to be 20pF and capacitance of third and fourth integrators was designed to be 1pF. The stage variable technique in the low power reconfigurable op-amp was used to solve the stability issue due to different capacitance loads for the reduction of KT/C noise. This technique enabled the proposed modulator to reduce the power consumption of 15% with respect to the conventional one. The proposed modulator was fabricated with 0.18um CMOS N-well 1 poly 6 metal process and consumes 305uW at supply voltage of 1.8V. The measurement results demonstrated that SNDR, ENOB, DR, FoM(Walden), and FoM(Schreier) were 66.3 dB, 10.6 bits, 83 dB, 98 pJ/step, and 142.8 dB at the sampling frequency of 256kHz, oversampling ratio of 128, clock frequency of 1.024 MHz, and input frequency of 250 Hz, respectively.