• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.562-564
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• 2004

캐시 선인출 기법은 메모리 참조에 따른 지연시간을 줄이는 효과적인 방법이다. 그러나 너무 적극적인 선인출은 캐시 오염을 유발시켜 선인출에 의한 장점을 상쇄시킨다. 본 연구에서는 캐시의 오염을 줄이기 위해 동적으로 필터 테이블을 참조하여 선인출 명령을 수행할 지의 여부를 결정하는 4가지 필터링 방법들을 비교 평가한다. 비교 연구를 위한 이상적인 필터링 구조를 제안하였으며, 기존 연구에서의 잠김 현상을 개선하기 위한 이진 상태 구조를 제안하였다. 또한, 정교한 필터링을 위한 블록주소 참조 방식을 제안하였다. 일반적으로 많이 사용되는 일반 벤치마크 프로그램과 멀티미디어 벤치마크 프로그램들에 대하여 실험한 결과, 캐시 미스율이 이진 상태 구조는 평균 5.6%, 블록주소 참조 구조는 7.9% 각각 감소하였다.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.5
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• pp.529-539
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• 2000

This paper proposes a prefetch-based disk buffer management algorithm, which we call W2R (Veighingjwaiting Room). Instead of using elaborate prefetching schemes to decide which blockto prefetch and when, we simply follow the LRU-OBL (One Block Lookahead) approach and prefetchthe logical next block along with the block that is being referenced. The basic difference is that theW2R algorithm logically partitions the buffer into two rooms, namely, the Weighing Room and theWaiting Room. The referenced, hence fetched block is placed in the Weighing Room, while theprefetched logical next block is placed in the Waiting Room. By so doing, we alleviate some inherentdeficiencies of blindly prefetching the logical next block of a referenced block. Specifically, a prefetchedblock that is never used may replace a possibly valuable block and a prefetched block, thoughreferenced in the future, may replace a block that is used earlier than itself. We show through tracedriven simulation that for the workloads and the environments considered the W2R algorithm improvesthe hit rate by a maximum of 23.19 percentage points compared to the 2Q algorithm and a maximumof 10,25 percentage feints compared to the LRU-OBL algorithm.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.1
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• pp.26-32
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• 2009

The multi-level storage architecture has been widely adopted in servers and data centers. However, while prefetching has been shown as a crucial technique to exploit sequentiality in accesses common for such systems and hide the increasing relative cost of disk I/O, existing multi-level storage studies have focused mostly on cache replacement strategies. In this paper, we show that prefetching algorithms designed for single-level systems may have their limitations magnified when applied to multi-level systems. Overly conservative prefetching will not be able to effectively use the lower-level cache space, while overly aggressive prefetching will be compounded across levels and generate large amounts of wasted prefetch. We design and implement a hierarchy-aware lower-level prefetching strategy called PMS(Prefetching strategy for Multi-level Storage system) that applicable to any upper level prefetching algorithms. PMS does not require any application hints, a priori knowledge from the application or modification to the va interface. Instead, it monitors the upper-level access patterns as well as the lower-level cache status, and dynamically adjusts the aggressiveness of the lower-level prefetching activities. We evaluated the PMS through extensive simulation studies using a verified multi-level storage simulator, an accurate disk simulator, and access traces with different access patterns. Our results indicate that PMS dynamically controls aggressiveness of lower-level prefetching in reaction to multiple system and workload parameters, improving the overall system performance in all 32 test cases. Working with four well-known existing prefetching algorithms adopted in real systems, PMS obtains an improvement of up to 35% for the average request response time, with an average improvement of 16.56% over all cases.

• Journal of KIISE
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• v.41 no.10
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• pp.832-837
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• 2014

Application loading speed can be improved by timely prefetching disk blocks likely to be needed by an application. However, existing prefetchers -- if they are not specialized to a particular application -- incur high overheads and are poor at identifying the blocks that will actually be required. There are many sequences in which blocks may be needed and, even if two access sequences are identical, block tracing and access timings can be affected significantly by the state of the buffer cache. We propose a new application-independent software-based prefetching technique, in which breakpoints are inserted at appropriate places in an application to collect the information on correlations between the blocks and to prefetch the potential blocks ahead of their schedule based on it. Experiments on an HDD-based desktop PC demonstrated an average 30% reduction in application launch time and 15% in general I/O, while reducing the wasted overhead.

• The KIPS Transactions:PartA
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• v.19A no.1
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• pp.35-44
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• 2012

Traditional technologies that are used to improve the performance of hard disk drives show many negative cases if they are applied to solid state drives (SSD). Access time and block sequence in hard disk drives that consist of mechanical components are very important performance factors. Meanwhile, SSD provides superior random read performance that is not affected by block address sequence due to the characteristics of flash memory. Practically, it is recommended to disable prefetching if a SSD is installed in a personal computer. However, this paper presents a combinational method of a prefetching scheme and a memory management that consider the internal structure of SSD and the characteristics of NAND flash memory. It is important that SSD must concurrently operate multiple flash memory chips. The I/O unit size of NAND flash memory tends to increase and it exceeded the block size of operating systems. Hence, the proposed prefetching scheme performs in an operating unit of SSD. To complement a weak point of the prefetching scheme, the proposed memory management scheme adaptively evicts uselessly prefetched data to maximize the sum of cache hit rate and prefetch hit rate. We implemented the proposed schemes as a Linux kernel module and evaluated them using a commercial SSD. The schemes improved the I/O performance up to 26% in a given experiment.