• Aerospace Engineering and Technology
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• v.13 no.2
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• pp.38-46
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• 2014

CRC (Cyclic Redundancy Codes) is a error detection method for the date transmission, which is applied to the GRDDP (GOES-R Reliable Data Delivery Protocol) between satellite and GEMS (Geostationary Environmental Monitoring Sensor) on the GEO-KOMPSAT 2B development. This paper introduces a principle of the table based CRC, and explains software implementation results of the CRC8 applied to GEMS.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.1
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• pp.83-91
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• 1993

In the digital transmission system, cyclic redundancy check(CRC) code is widely used because it is easy to be implemented and has good performance in error detection. CRC code generator consists of several shift registers and modulo 2 adders. After manipulation of input data stream in the encoder, the remaining value of shift registers becomes CRC code. At the receiving side, error can be detected and corrected by CRC codes immediately transmitted after data stream. But, in the high speed system such as an A TM switch, it is difficult to implement the serial CRC encoder because of speed limitation of available semiconductor devices. In this paper, we propose the efficient parallel CRC encoder and syndrome calculator to solve the speed problem in implementing these functions using the existing semiconductor technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.1
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• pp.109-117
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• 2013

Polar codes are the first provable error correcting code achieving the symmetric channel capacity in a wide case of binary input discrete memoryless channel(BI-DMC). However, finite length polar codes have an error floor problem with successive-cancellation list(SCL) decoder. From previous works, we can solve this problem by concatenating CRC(Cyclic Redundancy Check) codes. In this paper we propose to make polar codes having extended-minimum distance from original polar codes without outer codes using correlation with generate matrix of polar codes and that of RM(Reed-Muller) codes. And we compare performance of proposed polar codes with that of polar codes concatenating CRC codes.

• Journal of IKEEE
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• v.22 no.4
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• pp.896-900
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• 2018

Traditionally, Linear Shift Feedback Register (LFSR) has been widely employed to implement Cyclic Redundant Check (CRC) codes for a serial input. Since many applications including network and storage systems demand as high throughput as ever, various efforts have been made to implement CRC hardware to support parallel inputs. Among various parallel schemes, the look-ahead scheme is one of the most widely used schemes due to its short critical path. However, it is very cumbersome to design HDL codes for parallel CRC codes since the look-ahead scheme is inevitable to consider how register and input values move in the next cycles. Thus, this paper proposes a novel CRC hardware generator, which automatically produces HDL codes given a CRC polynomial and parallel factor. The experimental results verify the applicability to use the proposed generator by analyzing the synthesis results from the generated HDL code.

• The KIPS Transactions:PartC
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• v.11C no.3
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• pp.353-360
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• 2004

In this Paper, We propose an efficient iteration decoding control method with variable iteration decoding of iteration codes decoding using Cyclic Redundancy Check. As the number of iterations increases, the bit error rate and frame error rate of the decoder decrease and the incremental improvement gradually diminishes. However, when the iteration decoding number is increased, it require much delay and amount of processing time for decoding. Also, It can be observed the error nor that the performance cannot be improved even though increasing of the number of iterations and SNR. So, Suitable number of iterations for stopping criterion is required. we propose variable iteration control method to adapt variation of channel using Frame Error-Check indicator. Therefore, the amount of computation and the number of iterations required for iteration decoding with CRC method can be reduced without sacrificing performance.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.20-28
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• 2014

This paper proposes a faulty node detection scheme that performs collective monitoring of a distributed networked control systems using interval weighting factor. The algorithm is designed to observe every node's behavior collectively based on the pseudo-random Bose-Chaudhuri-Hocquenghem (BCH) code. Each node sends a single BCH bit simultaneously as a replacement for the cyclic redundancy check (CRC) code. The fault judgement is performed by performing sequential check of observed detected error to guarantee detection accuracy. This scheme can be used for detecting and preventing serious damage caused by node failure. Simulation results show that the fault judgement based on decision pattern gives comprehensive summary of suspected faulty node.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.8
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• pp.2013-2022
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• 1996

Cyclic Codes can be used for burs(or time slot) synchronization as well as error detection as that the overhead bits of the burst, which would be nessary to seperate burst synchronization and error detection systems, may be eliminated. In this paper a new method for combined burst synchronization and error detection is proposed which requires CRC decoding once only, while the previous method which inspects channel error after searching for burst synchronization requeires CRC decoding twice. The proposed method has the advantage of simple implementation and reducing processing time over the previous one, still showing the same detection perfdormance. It may occur that a burst different from the actually transmitted one is falsely accepted in the presence of channel errors. The exact expression for the false acceptance probability is newly presented through a simple derivation basied on the fact that it is determined by channel errors but not by detection methods.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.7
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• pp.3156-3167
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• 2020

One drawback of polar codes is that they are not universal, that is, to achieve optimal performance, different polar codes are required for different kinds of channel. This paper proposes a polar code construction scheme for Nakagami-m fading channel. The scheme fully considers the characteristics of Nakagami-m fading channel, and uses the optimized Bhattacharyya parameter bounds. The constructed code is applied to an orthogonal frequency division multiplexing (OFDM) system over Nakagami-m fading channel to prove the performance of polar code. Simulation result shows the proposed codes can get excellent bit error rate (BER) performance with successive cancellation list (SCL) decoding. For example, the designed polar code with cyclic redundancy check (CRC) aided SCL (L = 8) decoding achieves 1.1dB of gain over LDPC at average BER about 10^-5 under 4-quadrature amplitude modulation (4QAM) while the code length is 1024, rate is 0.5.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.2
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• pp.658-675
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• 2022

This paper presents a fast-simplified successive cancellation (SC) flipping (Fast-SSC-Flip) decoding algorithm for polar code. Firstly, by researching the probability distribution of the number of error bits in a node caused by channel noise in simplified-SC (SSC) decoder, a measurement criterion of node reliability is proposed. Under the guidance of the criterion, the most unreliable nodes are firstly located, then the unreliable bits are selected for flipping, so as to realize Fast-SSC-Flip decoding algorithm based on node reliability (NR-Fast-SSC-Flip). Secondly, we extended the proposed NR-Fast-SSC-Flip to multiple node (NR-Fast-SSC-Flip-ω) by considering dynamic update to measure node reliability, where ω is the order of flip-nodes set. The extended algorithm can correct the error bits in multiple nodes, and get good performance at medium and high signal-to-noise (SNR) region. Simulation results show that the proposed NR-Fast-SSC-Flip decoder can obtain 0.27dB and 0.17dB gains, respectively, compared with the traditional Fast-SSC-Flip [14] and the newly proposed two-bit-flipping Fast-SSC (Fast-SSC-2Flip-E2) [18] under the same conditions. Compared with the newly proposed partitioned Fast-SSC-Flip (PA-Fast-SSC-Flip) (s=4) [18], the proposed NR-Fast-SSC-Flip-ω (ω=2) decoder can obtain about 0.21dB gain, and the FER performance exceeds the cyclic-redundancy-check (CRC) aided SC-list (CRC-SCL) decoder (L=4).