• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.2
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• pp.36-43
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• 1985

This paper describes a DRC (Design Rule Check) algorithm and its program implement-ation which requires CPU time linearly proportional to the number of rectangular patterns n the NMOS If layout. While the CPU time for conventional DRC algorithm is proportion-al to 0(nlogn) or 0(n**1.2), (n:number of rectangles it was shown that the present also-rithm only consumes CPU time linearly proportional to 0(n).

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2000.11a
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• pp.229-232
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• 2000

This research aims at developing a low-cost PC-NC system based on one-CPU and investigating the feasibility of its application to a simple-function lathe. Its hardware consists a two axes motion control board including a 24bit counter, 8253 timer, a 12bit DA converter, DIO board for PLC operation and a PC with Intel Pentium 466MHz. The fundamental real-time MC functions such as G-code interpretation, interpolation, position and velocity control of axes are performed. User programming interface with functions of icon manipulation, tool-path simulation and NC-code generation was implemented. In order to achieve real-time control and safety, axis control, NC interpretation, interpolation and user communication are completely executed during every interrupt interval of I msec.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.35 no.10
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• pp.940-947
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• 2007

For the performance upgrade of a supersonic jet fighter, the processor and FLCC(Flight Control Computer) Architecture were upgraded from a baseline FLCC. Prior to the hardware implementation phase, the exact CPU throughput estimation is necessary. For this purpose, an experimental method for new FLCC throughput estimation was introduced in this study.　While baseline FLCC operating, the CPU address bus was collected with logic analyzer, and then decoded to get the exact access times to each memory-memory and the number of program Instruction branches. Based on these data, a throughput test in CPU demo-board of the new FLCC configuration was performed. From test results, the CPU-Memory architecture was design-changed before FLCC hardware implementation phase. To check the flight stability degradation due to power-interrupt problem due to CPU-Memory architecture change, the piloted HILS (Hardware-In-the Loop Simulator) test was conducted.

• KIISE Transactions on Computing Practices
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• v.20 no.9
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• pp.507-512
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• 2014

Recently, Distributed computing processing begins using both CPU(Central processing unit) and GPU(Graphic processing unit) to improve the performance to overcome darksilicon problem which cannot use all of the transistors because of the electric power limitation. There is an integrated graphics processor that CPU and GPU share memory and Last level cache(LLC). But, There is no LLC access rules between CPU and GPU, so if GPU and CPU processes run together at the same time, performance of both processes gets worse because of the contention on the LLC. This Paper gives evidence to prove the need of the Cache Partitioning and is mentioned about the cache partitioning design using page coloring to allocate the L3 Cache space only for the GPU process to guarantee GPU process performance.

• Journal of applied mathematics & informatics
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• v.2 no.2
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• pp.21-46
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• 1995

Congestion and memory occupancy in computer system may be reduced further if new jobs are admitted only when the num-ber of jobs queued at CPU is below CPU run queue cutoff (RQ). In this paper we prove that response time of a job is invariant with respect to RQ if jobs do not communicate each other. We also demonstrate this invariance property numerically using marix-geometric methods and present an approximate method for the delay due to context switch-ing under time slicing. The approximation suggests that time slicing with constant overhead yields a throughput similar to an FCFS system without overhead.

• KIISE Transactions on Computing Practices
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• v.23 no.7
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• pp.452-457
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• 2017

Linux is a general-purpose operating system that supports several schedulers, allowing different schedulers to coexist. In addition, Linux uses the Control Group (cgroup) to reserve CPU resources for task groups that follow the real-time (SCHED_FIFO, SCHED_RR) and non-real-time (SCHED_NORMAL) scheduler policies, except for the deadline scheduler (SCHED_DEADLINE). The cgroup performs the schedulability analysis to guarantee the reserved CPU resource as much as possible. However, current implementation of the schedulability analysis does not distinguish between deadline tasks and real-time tasks. Therefore, if these deadline tasks and real-time task groups coexist, there is a case where the resource reservation for the real-time task group is rejected. In this paper, we analyze the problems in the schedulability analysis for real-time task groups of Linux cgroups and propose patches to solve these problems.

• Journal of the Korea Society of Computer and Information
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• v.29 no.1
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• pp.1-9
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• 2024

This paper proposes an integration of the ED-H scheduling algorithm, known for optimal real-time scheduling, with the LoRaEnergySim simulator. This integration facilitates the simulation of interactions between real-time scheduling algorithms for tasks with time constraints in Class-A LoRaWAN Class-A devices using a super-capacitor-based energy harvesting system. The time and energy characteristics of LoRaWAN status and state transitions are extracted in a log format, and the task model is structured to suit the time-slot-based ED-H scheduling algorithm. The algorithm is extended to perform tasks while satisfying time constraints based on CPU executions. To evaluate the proposed approach, the ED-H scheduling algorithm is executed on a set of tasks with varying time and energy characteristics and CPU occupancy rates ranging from 10% to 90%, under the same conditions as the LoRaEnergySim simulation results for packet transmission and reception. The experimental results confirmed the applicability of co-simulation by demonstrating that tasks are prioritized based on urgency without depleting the supercapacitor's energy to satisfy time constraints, depending on the scheduling algorithm.

• Proceedings of the Korean Information Science Society Conference
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• 2010.06b
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• pp.497-502
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• 2010

조합형 실시간 스케줄링은 계층적으로 구성된 실시간 시스템에 대해 실시간성을 보장할 수 있는 방법을 제공한다. 조합형 스케줄링 이론을 통해 여러 개의 실시간 태스크를 하나의 실시간 태스크로 묶어 스케줄링 할 수 있으며, 실시간 보장을 위해 필요한 CPU 요구량을 계산하였다. 하지만, 양자화에 대한 고려가 없어, 틱-기반 스케줄링 시스템에서 정확한 CPU 요구량을 계산할 수 없다. 따라서, 본 연구에서는 양자화에 따른 CPU 할당량의 영향을 정량적으로 보여준다.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.04a
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• pp.31-32
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• 2014

다중의 명령어를 동시에 수행할 수 있는 멀티코어 시스템의 특성으로 하나의 시스템 내에서 태스크를 수행하면서 외부 이벤트의 발생에 의한 인터럽트를 동시에 처리할 수 있다. 각 태스크가 처리되어야 하는 시간에 제약성을 갖는 실시간 시스템에서는 스케줄러에 의해 CPU 코어에서의 수행이 제어되어야한다. 본 논문에서는 최적이라고 알려진 Pfair 멀티코어 스케줄러의 각 코어별 유휴시간을 정량적으로 평가함으로써 인터럽트 처리의 지연시간을 분석한다.

• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.9-18
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• 2002

In this paper, we propose scalable scheduling techniques based on EDF to efficiently integrate hard real-time and multimedia soft real-time tasks in the distributed real-time multimedia database system. Hard tasks are guarangteed based on worst case execution times, whereas multimedia soft tasks are served based on mean execution times. This paper describes a served-based scheme for partitioning the CPU bandwidth among different task classes that coexist in the same system. To handle the problem of class overloads characterized by varying number of tasks and varying task arrival rates, thus scheme shows how to adjust the fraction of the CPU bandwidth assigned to each class. This scheme fixes the maximum time that each hard task can execute in the period of the server, whereas it can dynamically change the bandwidth reserved to each multimedia task. The proposed method is capable of minimizing the mean tardiness of multimedia tasks, without jeopardizing the schedulability of the hard tasks. The performance of this scheduling method is compared with that of similar mechanisms through simulation experiments.