• 한국산학기술학회:학술대회논문집
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• 한국산학기술학회 2006년도 추계학술발표논문집
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• pp.272-275
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• 2006

본 논문에서는 CMP(Chemical Mechanical Polishing) 슬러리용으로 사용되는 저가이면서 입도 분포가 균일한 콜로이달 실리카(Colloidal Silica)를 사용하여 추가의 첨가제 없이 열처리 공정만을 거쳐 석영유리를 제조하여 6N의 순도와 1 mm 두께 기준 86%의 자외선 투과율 그리고 AFM(Atomic Force Microscopy) 및 간섭계 현미경을 이용하여 표면의 거칠기가 1 nm 미만인 고순도 석영유리를 제조하였다.

• 반도체디스플레이기술학회지
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• 제20권2호
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• pp.103-108
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• 2021

The TCD is used as one of the indicators for determining whether TSV Hole is defective. If the TCD is not normal size, it can lead to contamination of the CMP equipment or failure to connect the upper and lower chips. We propose a deep learning model for measuring the TCD. To verify the performance of the proposed model, we compared the prediction results of the proposed model for 2461 via holes with the CD-SEM measurement data and the prediction results of the existing model. Although the number of trainable parameters in the proposed model was about one two-thousandth of the existing model, the results were comparable. The experiment showed that the correlation between CD-SEM and the prediction results of the proposed model measured 98%, the mean absolute difference was 0.051um, the standard deviation of the absolute difference was 0.045um, and the maximum absolute difference was 0.299um on average.

• 한국윤활학회:학술대회논문집
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• 한국윤활학회 2002년도 proceedings of the second asia international conference on tribology
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• pp.435-437
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• 2002

Polishing of copper, a process called copper chemical mechanical polishing, is a critical, intermediate step in the planarization of silicon wafers. During polishing, the electrodeposited copper films are removed by slurries: and the differential polishing rates between copper and the surrounding silicon dioxide leads to a greater removal of the copper. The differential polishing develops dimples and furrows; and the process is called dishing and erosion. In this work, we present the results of experiments on dishing and erosion of copper-CMP, using patterned silicon wafers. Results are analyzed for the pattern factors and properties of the copper layers. Three types of pads - plain, perforated, and grooved - were used for polishing. The effect of slurry chemistries and pad soaking is also reported.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.171-175
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• 2001

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectrics and metal, which can apply to employed in integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of free-defects in inter level dielectrics and metal. Especially, defects like (micro-scratch) lead to severe circuit failure, and affects yield. Current conditioning method - bladder type, orbital pad motion - usually provides unsuitable pad profile during ex-situ conditioning near the end of pad life. Since much of the pad wear occurs by the mechanism of bladder tripe conditioning and its orbital motion without rotation, we need to implement new ex-situ conditioner which can prevent abnormal regional force on pad caused by bladder-type and also need to rotate the pad during conditioning. Another important study of ADPC is related to the orbital scratch of which source is assumed as diamond grit dropped from the strip during ex-situ conditioning. Scratch from diamond grit damaged wafer severely so usual1y scraped. Figure 1 shows the typical shape of scratch damaged from diamond. We suspected that intensive forces to the edge area of bladder type stripper accelerated the drop of Diamond grit during conditioning, so new designed Flat stripper was introduced.

• 한국식품과학회지
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• 제28권1호
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• pp.152-156
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• 1996

우리나라 고유의 전통 조미식품인 고추장의 품질개선과 담금 방법을 과학적으로 표준화하기 위하여 전국의 각 가정에서 담은 55점의 전통 고추장을 수집하여 맛성분 특성을 조사하였다. 고추장의 유리당은 glucose $(8.21{\pm}5.62%)$와 maltose $(6.95{\pm}7.27%)$가 대부분이고 fructose $(1.88{\pm}1.27%)$와 sucrose $(1.05{\pm}1.21%)$가 소량 존재하였다. 유기산은 succinic acid $(901.83{\pm}826.23\;mg%)$, citric acid $(484.16{\pm}242.89\;mg%)$, lactic acid $(381.63{\pm}367.88\;mg%)$ 함량이 많았고 acetic acid, oxalic acid, formic acid는 소량 존재하였다. 고추장 중의 총 유리 아미노산은 64.35 mg%이었으며, proline $(10.66{\pm}6.27\;mg%)$, glutamic acid $(9.27{\pm}10.97\;mg%)$, aspartic acid $(9.14{\pm}5.84\;mg%)$, lysine $(6.19{\pm}6.66\;mg%)$, serine $(5.72{\pm}3.79\;mg%)$함량이 많았다. 핵산 관련물질은 CMP가 $42.90{\pm}28.16\;mg%$으로 가장 많았고, 다음으로 hypoxanthine $(6.86{\pm}3.45\;mg%)$, IMP $(5.59{\pm}5.84\;mg%)$, inosine $(4.58{\pm}6.91\;mg%)$, GMP $(3.36{\pm}3.93\;mg%)$순이었으며 AMP나 UMP는 소량 존재하였다.

• ETRI Journal
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• 제40권6호
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• pp.759-773
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• 2018

Uncore components such as on-chip memory systems and on-chip interconnects consume a large amount of energy in emerging embedded applications. Few studies have focused on next-generation analytical models for future chip-multiprocessors (CMPs) that simultaneously consider the impacts of the power consumption of core and uncore components. In this paper, we propose a convex-optimization approach to design heterogeneous uncore architectures for embedded CMPs. Our convex approach optimizes the number and placement of memory banks with different technologies on the memory layer. In parallel with hybrid memory architecting, optimizing the number and placement of through silicon vias as a viable solution in building three-dimensional (3D) CMPs is another important target of the proposed approach. Experimental results show that the proposed method outperforms 3D CMP designs with hybrid and traditional memory architectures in terms of both energy delay products (EDPs) and performance parameters. The proposed method improves the EDPs by an average of about 43% compared with SRAM design. In addition, it improves the throughput by about 7% compared with dynamic RAM (DRAM) design.

• 한국지구물리탐사학회:학술대회논문집
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• 한국지구물리탐사학회 2008년도 공동학술대회
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• pp.107-112
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• 2008

동해가스전과 같이 해저면 심부에 위치한 저류층의 경우 CMP 단면도 상에서 AVO 반응을 관찰하기가 어려운 경우가 종종 발생한다. 이렇게 심부저류층인 경우 고결성이 증가하기 때문에 매질의 공극유체가 가스로 치환되더라도 매질의 P파 속도가 크게 감소하지 않으며 이로 인해 AVO 반응 확인이 어렵다. 본 연구에서는 상.하부층의 포아송비를 달리하면서 포아송비의 차이가 작아질수록 입사각에 따른 반사진폭의 변화량이 작아져 AVO 반응이 미미해짐을 관찰하였다. 이 결과를 토대로 동해가스전의 AVO 반응의 한계점을 고찰하기 위해서 탄성파 자료와 물리검층 자료를 이용하여 고래 V 구조를 모사한 속도모델을 만들고 합성탄성파 탐사자료를 생성하였다. 매질의 성질을 이용하여 이론적으로 계산한 AVO 반응과 실제 합성탄성파 자료를 처리하여 얻은 AVO 반응을 비교한 결과, 상.하부층의 포아송비의 차이가 작을 경우 입사각에 따른 반사진폭 변화가 매우 작으며 잡음이나 전처리 과정 중에서 발생하는 진폭 왜곡에 의해 AVO 반응 특성이 가려짐을 확인할 수 있었다. 이러한 심부저류층의 AVO 분석의 한계점을 극복하기 위해서는 자료취득 단계부터 정확한 반사파 진폭을 획득해야 하며 자료처리 과정에서도 반사파 진폭을 보존할 수 있는 기술이 필요하다.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2007년도 춘계학술대회B
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• pp.2449-2452
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• 2007

Hot spots on thin wafers of IC packages are becoming important issues in thermal and electrical engineering fields. To investigate these hot spots, we developed a Diode Temperature Sensor Array (DTSA) that consists of an array of 32 ${\times}$32 diodes (1,024 diodes) in a 8 mm ${\times}$ 8 mm surface area. To know specifically the hot spot temperature which is affected by the chip thickness and a generated power, we made the DTSA chips, which have 21.5 ${\mu}m$, 31 ${\mu}m$, 42 ${\mu}m$, 100 ${\mu}m$, 200 ${\mu}m$, and 400 ${\mu}m$ thickness using the CMP process. And we conducted the experiment using various heater power conditions (0.2 W, 0.3 W, 0.4 W, 0.5 W). In order to validate experimental results, we performed a numerical simulation. Errors between experimental results and numerical data are less than 4%. Finally, we proposed a correlation for the hot spot temperature as a function of the generated power and the wafer thickness based on the results of the experiment. This correlation can give an easy estimate of the hot spot temperature for flip chip packaging when the wafer thickness and the generated power are given.

• 대한기계학회논문집A
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• 제28권1호
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• pp.85-91
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• 2004

The sapphire wafers for blue light emitting devices were manufactured by the implementation of the surface machining technology based on micro-tribology. This process has been performed by chemical and mechanical polishing process. The sapphire crystalline wafers were characterized by double crystal X-ray diffraction. The sample quality of sapphire crystalline wafer at surfaces has a full width at half maximum of 89 arcsec. The surfaces of sapphire wafer were mechanically affected by residual stress during the polishing process. The wave pattern of optical interference of sapphire wafer implies higher abrasion rate in the edge of the wafer than its center from the Newton's ring.

• Journal of Information Display
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• 제3권3호
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• pp.35-43
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• 2002

Silicon-based 0.69-inch AMOEL microdisplay with integrated driver and timing controller circuits for microdisplay applications has been developed using 0.35 ${\mu}m$ l-poly 4-metal standard CMOS process with 5 V CMOS devices and CMP (Chemical Mechanical Polishing) technology. To reduce the large data programming time consumed in a conventional current programming pixel circuit technique and to achieve uniform display, de-amplifying current mirror pixel circuit and the current-mode data driver circuit with threshold roltage compensation are proposed. The proposed current-mode data driver circuit is inherently immune to the ground-bouncing effect. The Monte-Carlo simulation results show that the proposed current-mode data driver circuit has channel-to-channel non-uniformity of less than ${\pm}$0.6 LSB under ${\pm}$70 mV threshold voltage variaions for both NMOS and PMOS transistors, which gives very good display uniformity.