• Journal of Applied Reliability
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• v.16 no.1
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• pp.26-31
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• 2016

Purpose: The purpose of this study was to investigate the effect of grinding process and thickness on the fracture strength of silicon die used for semiconductor substrate. Method: Silicon wafers with different thickness from $200{\mu}m$ to $50{\mu}m$ were prepared by chemical mechanical polishing (CMP) and dicing before grinding (DBG) process, respectively. Fracture load was measured by point load test for 50 silicon dies per each wafer. Results: Fracture strength at the center area was lower than that at the edge area of the wafer fabricated by DBG process, while random distribution of the fracture strength was observed for the CMPed wafer. Average fracture strength of DBGed specimens was higher than that of the CMPed ones for the same thickness of wafer. Conclusion: DBG process can be more helpful for lowering fracture probability during the semiconductor fabrication process than CMP process.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2004.11a
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• pp.331-338
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• 2004

We present a three-dimensional average flow model considering elastic deformation of pad asperities for chemical mechanical planarization. To consider the contact deformation of pad asperities in the calculation of the flow factor, three-dimensional contact analysis of a semi-infinite solid based on the use of influence functions is conducted from computer generated three dimensional roughness data. The average Reynolds equation and the boundary condition of both force and momentum balance are used to investigate the effect of pad roughness and external pressure conditions on film thickness and wafer position angle.

• Transactions on Electrical and Electronic Materials
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• v.6 no.5
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• pp.225-228
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• 2005

In this work, we studied the optimized copper thickness in Cu ECP (Electrochemical Plating). In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge (bump, hump or over-plating amount), Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness. In the aspect of bump and dishing, the bulge increased according as target plating thickness decreased. Dishing of edge was larger than center of wafer. Also in case of electrical property, metal line resistance distribution became broad gradually according as Cu ECP thickness decreased. In conclusion, at least $20\%$ reduced Cu ECP thickness from current baseline; $0.8\;{\mu}m$ and $1.0\;{\mu}m$ are suitable to be adopted as newly optimized Cu ECP thickness for local and intermediate layer.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 1999.10a
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• pp.525-529
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• 1999

A cone shape drum polisher was developed to make up for the demerits of conventional CMP apparatus. The developed equipment has several superiorities. First of all, it can achieve uniform velocity profile on all the contact line because of its shape and easy to control the amount of slurry at the position of use. The whole area of wafer surface is exposed to the visual area except the contact line between wafer and drum, hence we can detect polishing end point more easily than any other polishing equipments. Also it has additional merits such as small foot print and polishing load. Polishing characteristics were investigated by developed equipment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05b
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• pp.31-34
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• 2003

The sapphire wafers for blue light emitting devices were manufactured by the implementation of the surface machining technology based on micro-tribology. This process has been performed by chemical and mechanical polishing(CMP) process. The sapphire crystalline wafers were characterized by double crystal X-ray diffraction. The sample quality of sapphire crystalline wafer at surfaces has a full width at half maximum 89 arcses. The surfaces of sapphire wafers were mechanically affected by residual stress and surface default. Sapphire wafers's waveness has higher abrasion rate in the edge of the wafer than its center due to Newton's Ring interference.

• Journal of Electrical Engineering and Technology
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• v.13 no.2
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• pp.886-891
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• 2018

Colloid silica using as abrasive for polishing sapphire has been extensively studied, which mechanism has also been deeply discussed. However, by the requirement of application enlargement and cost reduction, some new problems appear such as silica service life time, particle diameter mixing, etc. In this paper, several influences of colloid silica usage on sapphire CMP are examined. Results show particle diameter and concentration, pH value, service life time, particle diameter mixing heavily influence removal rate. Further analysis discloses there are two main effect aspects which are quantity of hydroxyl group, contact area for abrasive density stacking between abrasive and sapphire. Based on the discussions, a dynamic process of sapphire polishing is proposed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.93-94
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• 2005

Cu metallization using electrochemical plating(ECP) has played an important role in back end of line(BEOL) interconnect formation. In this work, we studied the optimized copper thickness using Bottom-up Gap-fill in Cu ECP, which is closely related with the pattern dependencies in Cu ECP and Cu dual damascene process at 0.13 ${\mu}m$ technology node. In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge, Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.57-58
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• 2006

Chemical-mechanical planarization (CMP) of Cu has used currently in semiconductor process for multilevel metallization system. This process requires the application of a considerable down-pressure to the sample in the polishing, because porous low-k films used in the Cu-multilevel interconnects of 65nm technology node are often damaged by mechanical process. Also, it make possible to reduce scratches and contaminations of wafer. Electrochemical mechanical planarization (ECMP) is an emerging extension of CMP. In this study, the electrochemical mechanical polisher was manufactured. And the static and dynamic potentiodynamic curve of Cu were measured in KOH based electrolyte and then the suitable potential was found.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.61-66
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• 2012

Chemical Mechanical Planarization (CMP) is a polishing process used in the microelectronic fabrication industries to achieve a globally planar wafer surface for the manufacturing of integrated circuits. Pad conditioning plays an important role in the CMP process to maintain a material removal rate (MRR) and its uniformity. For metal CMP process, highly acidic slurry containing strong oxidizer is being used. It would affect the conditioner surface which normally made of metal such as Nickel and its alloy. If conditioner surface is corroded, diamonds on the conditioner surface would be fallen out from the surface. Because of this phenomenon, not only life time of conditioners is decreased, but also more scratches are generated. To protect the conditioners from corrosion, thin organic film deposition on the metal surface is suggested without requiring current conditioner manufacturing process. To prepare the anti-corrosion film on metal conditioner surface, vapor SAM (self-assembled monolayer) and FC (Fluorocarbon) -CVD (SRN-504, Sorona, Korea) films were prepared on both nickel and nickel alloy surfaces. Vapor SAM method was used for SAM deposition using both Dodecanethiol (DT) and Perfluoroctyltrichloro silane (FOTS). FC films were prepared in different thickness of 10 nm, 50 nm and 100 nm on conditioner surfaces. Electrochemical analysis such as potentiodynamic polarization and impedance, and contact angle measurements were carried out to evaluate the coating characteristics. Impedance data was analyzed by an electrical equivalent circuit model. The observed contact angle is higher than 90o after thin film deposition, which confirms that the coatings deposited on the surfaces are densely packed. The results of potentiodynamic polarization and the impedance show that modified surfaces have better performance than bare metal surfaces which could be applied to increase the life time and reliability of conditioner during W CMP.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.362-363
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• 2005

The objectives of this paper are to achieve good planarization of the deposited film and to improve deposition efficiency of multi-layer structures by using surface-micromaching process in MEMS technology. Planarization characteristic of poly-Si film deposited on thin oxide layer with MEMS structures is evaluated with different slurries. Patterns used for this research have shapes of square, density, line, hole, pillar, and micro engine part. Advantages and disadvantages of CMP for MEMS structures are observed respectively by using the test patterns with structures larger than 1 um line width. Preliminary tests for material selectivity of poly-Si and oxide are conducted with two types of slurries: ILD1300 and Nalco2371. And then, the experiments were conducted based on the pretest.