• Journal of Advanced Navigation Technology
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• v.13 no.1
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• pp.48-53
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• 2009

The CMOS RF front-end for Global Positioning System(GPS)are implemented in 1P8M CMOS $0.13{\mu}m$ process. The LNAs consist of LNA1 with high gain and low NF, and LNA2 with low gain and high IIP3 for supporting operation with active and passive antenna. the measured performances of both LNAs are 16.4/13.8 dB gain, 1.4/1.68 dB NF, and -8/-4.4 dBm IIP3 with 3.2/2 mA form 1.2 V supply, respectively. The quadrature downconversion mixer is followed by transimpedance amplifier with gain controllability from 27.5 to 41 dB. The front-end performances in LNA1 mode are 39.8 dB conversion gain, 2.2 dB NF, and -33.4 dBm IIP3 with 6.6 mW power consumption.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.5
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• pp.109-114
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• 2023

In this paper, a 2-channel Image-Reject receiver using a 65-nm CMOS process is presented for Ka-band compact radars. The designed receiver consists of Low-Noise Amplifier (LNA), IQ mixer, and Analog Baseband (ABB). ABB includes a complex filter in order to suppress unwanted images, and the variable gain amplifiers (VGAs) in RF block and ABB have gain tuning range from 4.5-56 dB for wide dynamic range. The gain of the receiver is controlled by on-chip SPI controllers. The receiver has noise figure of <15 dB, OP1dB of >4 dBm, image rejection ratio of >30 dB, and channel isolation of >45 dB at the voltage gain of 36 dB, in the Ka-band target frequency. The receiver consumes 420 mA at 1.2 V supply with die area of 4000×1600 ㎛.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2011.06a
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• pp.197-197
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• 2011

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.91-95
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• 2003

In this work, we have designed Gilbert cell downconversion mixer using 0.25um Anam CMOS process, we also have analyzed Conversion gain and IIP3 using Taylor series in our own unique way. Especially, bulk terminal is used as LO( Local Oscillator) input for reduction of power consumption and supply voltage. Supply voltage used in this design is lower than 1.8V and core current is less than 500uA. The simulation experiments showed that the conversion gain, IIP3, and power consumption were -1dB, 4.46dBm, and 0.8mW, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5A
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• pp.482-489
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• 2010

In this paper we have proposed a new architecture of DQ-IRM(Double-Quadrature Image Rejection Mixer) for image rejection in the low-IF receiver. It consist of a frequency-tunable RF PPF(Poly Phase Filter) and the quadrature mixers. The conventional DQ-IRM generates the quadrature RF signals for the RF wide band at once. But the proposed DQ-IRM with the frequency-tuable RF PPF generates the quadrature RF signals for the narrow band of 2~3 channels bandwidth, which is partitioned from the RF wide band. We designed the CMOS RF tuner for T-DMB(Terrestrial Digital Multimedia Broadcasting) with the proposed 3rd DQ-IRM using a 0.18um CMOS technology and verified the performances of the designed receiver such as the image rejection ratio, the noise figure and the power consumption. The overall NF of the RF tuner is about 1.26 dB and the image reject ratio is about 51 dB. The power consumption is 55.8 mW at 1.8 V supply voltage. The chip area is $3.0{\times}2.5mm^2$.

• International journal of advanced smart convergence
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• v.10 no.1
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• pp.12-23
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• 2021

This paper proposes a low power radio frequency receiver front-end where, in a single stage, single-balanced mixer and voltage-controlled oscillator are stacked on top of low noise amplifier and re-use the dc current to reduce the power consumption. In the proposed topology, the voltage-controlled oscillator itself plays the dual role of oscillator and mixer by exploiting a series inductor-capacitor network. Using a 65 nm complementary metal oxide semiconductor technology, the proposed radio frequency front-end is designed and simulated. Oscillating at around 2.4 GHz frequency band, the voltage-controlled oscillator of the proposed radio frequency front-end achieves the phase noise of -72 dBc/Hz, -93 dBc/Hz, and -113 dBc/Hz at 10KHz, 100KHz, and 1 MHz offset frequency, respectively. The simulated voltage conversion gain is about 25 dB. The double-side band noise figure is -14.2 dB, -8.8 dB, and -7.3 dB at 100 KHz, 1 MHz and 10 MHz offset. The radio frequency front-end consumes only 96 ㎼ dc power from a 1-V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.670-680
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• 2010

A low power single-chip CMOS receiver for 60 GHz mobile application are proposed in this paper. The single-chip receiver consists of a 4-stage current re-use LNA with under 4 dB NF, Cgs compensating resistive mixer with -9.4 dB conversion gain, Ka-band low phase noise VCO with -113 dBc/Hz phase noise at 1 MHz offset from 26.89 GHz, high-suppression frequency doubler with -0.45 dB conversion gain, and 2-stage current re-use drive amplifier. The size of the fabricated receiver using a standard 0.13 ${\mu}m$ CMOS technology is 2.67 mm$\times$0.75 mm including probing pads. An RF bandwidth is 6.2 GHz, from 55 to 61.2 GHz and an LO tuning range is 7.14 GHz, from 48.45 GHz to 55.59 GHz. The If bandwidth is 5.25 GHz(4.75~10 GHz) The conversion gain and input P1 dB are -9.5 dB and -12.5 dBm, respectively, at RF frequency of 59 GHz. The proposed single-chip receiver describes very good noise performances and linearity with very low DC power consumption of only 21.9 mW.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.443-444
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• 2008

A double-balanced frequency up-converter using the Gilbert cell structure has been designed with the TSMC $0.18\;{\mu}m$ CMOS library. The frequency up-converter consists of a Mixer core and IF / LO balun. Frequency Up-converter exhibits a 3.4 dB conversion gain with a - 7.6 dBm $P_{1dB}$ for IF power of -10 dBm and LO power of 0 dBm inputs. It also exhibits 92.2 % modulation depth as a ASK modulator.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.617-618
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• 2006

A CMOS quadrature Up-converter for a direct-conversion receiver of 5.15-5.825GHz wireless LAN is described. The Up-converter consists of two sub-harmonic mixers, for I and Q channels, and an LO generation network. In order to decrease the number of inductor, I and Q path are merged. The simulation results including all the parasitics show -17.3dB conversion gain at center and -8 dBv oIP3 while consuming 22.968mW under 1.8V supply. The quadrature Up-converter is under fabrication with the other transmitter blocks in a $0.18{\mu}m$ CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.1
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• pp.59-64
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• 2011

A low noise and low power RF front-end for 5.8 GHz DSRC (Dedicated Short Range Communication) receiver is presented. The RF front-end is composed of a single-to-differential two-stage LNA and a Gilbert down-conversion mixer. In order to remove an external balun and 5.8 GHz LC load tuning circuit, a single-to-differential LNA with capacitive cross coupled pair is proposed. The RF front-end is fabricated in a 0.13 ${\mu}m$ CMOS process and draws 7.3 mA from a 1.2 V supply voltage. It shows a voltage gain of 40 dB and a noise figure (NF) lower than 4.5 dB over the entire DSRC band.