• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.12
• /
• pp.20-27
• /
• 1997

In this paper, a multiplying digital-to-analog converter (MDAC) circuit for low-power high-resolution CMOS algorithmic A/D converters (ADC's) is proposed. The proposed MDAC is designed to operte properly at a supply at a supply voltge between 3 V and 5 V and employs an analog0domain power reduction technique based on a bias switching circuit so that the total power consumption can be optimized. As metal-to-metal capacitors are implemented as frequency compensation capacitors, opamps' performance can be varied by imperfect process control. The MDAC minimizes the effects by the circuit performance variations with on-chip tuning circuits. The proposed low-power MDAC is implementd as a sub-block of a 10-bit 200kHz algorithmic ADC using a 0.6 um single-poly double-metal n-well CMOS technology. With the power-reduction technique enabled, the power consumption of the experimental ADC is reduced from 11mW to 7mW at a 3.3V supply voltage and the power reduction ratio of 36% is achieved.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.32B no.11
• /
• pp.1434-1444
• /
• 1995

Current test has recently been known to be a promising testing method in CMOS VLSI because conventional voltage test can not make sure of the complete detection of bridging, gate-oxide shorts, stuck-open faults and etc. This paper presents a new BIC(built-in current sensor) for the internal current test in CMOS logic circuit. A single phase clock is used in the BIC to reduce the control circuitry of it and to perform a self- testing for a faulty current. The BIC is designed to detect the faulty current at the end of the clock period, so that it can test the CUT(circuit under test) with much longer critical propagation delay time and larger area than conventional BICs. The circuit is composed of 18 devices and verified by using the SPICE simulator.

• Transactions on Electrical and Electronic Materials
• /
• v.8 no.1
• /
• pp.21-25
• /
• 2007

A two-dimensional TCAD MEDICI simulator was used to examine the voltage transfer characteristics, on-off switching properties and latch-up of a CMOS inverter as a function of the n-channel length and doping levels. The channel in a LDMOSFET encloses a junction-type source and is believed to be an important parameter for determining the circuit operation of a CMOS inverter. The digital logic levels of the output and input voltages were analyzed from the transfer curves and circuit operation. The high and low logic levels of the input voltage showed a strong dependency on the channel length, while the lateral substrate resistance from a latch-up path in the CMOS inverter was comparable to that of a typical CMOS inverter with a guard ring.

• Journal of IKEEE
• /
• v.8 no.1 s.14
• /
• pp.54-62
• /
• 2004

In this paper, we discuss on the design of a current mode CMOS multiplier circuit over $GF(3^m)$. Using the standard basis, we show the variation of vector representation of multiplicand by multiplying primitive element α, which completes the multiplicative process. For the $GF(3^m)$ multiplicative circuit design, we design GF(3) adder and multiplier circuit using current mode CMOS technology and get the simulation results. Using the basic gates - GF(3) adder and multiplier, we build the $GF(3^m)$ multiplier circuit and show the examples for the case m=3. We also propose the assembly of the operation blocks for a complete $GF(3^m)$ multiplier. Therefore, the proposed circuit is easily extensible to other p and m values over $GF(p^m)$ and has advantages for VLSI implementation. We verify the validity of the proposed circuit by functional simulations and the results are provided.

• Journal of IKEEE
• /
• v.18 no.4
• /
• pp.586-592
• /
• 2014

In this paper, high efficiency power management IC(PMIC) with DT-CMOS(Dynamic threshold voltage Complementary MOSFET) switching device is presented. PMIC is controlled PWM control method in order to have high power efficiency at high current level. The DT-CMOS switch with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuit consist of a saw-tooth generator, a band-gap reference(BGR) circuit, an error amplifier, comparator circuit, compensation circuit, and control block. The saw-tooth generator is made to have 1.2MHz oscillation frequency and full range of output swing from supply voltage(3.3V) to ground. The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on current mode PWM control circuits and low on-resistance switching device, achieved the high efficiency nearly 96% at 100mA output current. And Buck converter is designed along LDO in standby mode which fewer than 1mA for high efficiency. Also, this paper proposes two protection circuit in order to ensure the reliability.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.24 no.5
• /
• pp.457-461
• /
• 2014

Using $0.18{\mu}m$ CMOS process silicon neuron circuit of the pulse type for modeling biological neurons, were designed in the semiconductor integrated circuit. Neuron circuiSt providing is formed by MOS switch for initializing the input terminal of the capacitor to the input current signal, a pulse signal and an amplifier stage for generating an output voltage signal. Synapse circuit that can convert the current signal output of the input voltage signal, using a bump circuit consisting of NMOS transistors and PMOS few. Configure a chain of neurons for verification of the neuron model that provides synaptic neurons and two are connected in series, were performed SPICE simulation. Result of simulation, it was confirmed the normal operation of the synaptic transmission characteristics of the signal generation of nerve cells.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.44 no.1
• /
• pp.32-37
• /
• 2007

A DMB CMOS power amplifier (PA) with high efficiency and linearity is present. For this work, a 0.13-um standard CMOS process is employed and all components of the proposed PA are fully integrated into one chop including output matching network and adaptive bias control circuit. To improve the efficiency and linearity simultaneously, an adaptive bias control circuit is adopted along with second harmonic termination circuit at the drain node. The PA is shown a $P_{1dB}$ of 16.64 dBm, power added efficiency (PAE) of 38.31 %, and power gain of 24.64 dB, respectively. The third-order intermodulation (IMD3) and the fifth-order intermodulation (IMD5) have been -24.122 dBc and -37.156 dBc, respectively.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.212-214
• /
• 2005

The charge-pump circuit which is used to generate higher voltage than the available supply voltage has wide applications such as the flash memory of EEPROM Because the demand for high voltage comes from physical mechanism such as the oxide tunneling, the required pumped voltage cannot be scaled as the power supply voltage is scaled. Therefore, an efficient charge-pump circuit that can achieve high voltage from the available low supply voltage is essential. A new Analog Switch p-well CMOS charge pump circuit without the MOS device body effect is processed. By improve the structure of the circuit's transistors to reduce the threshold voltage shift of the devices, the threshold voltage of the device is kept constant. So, the circuit electrical characteristics are higher output voltage within a shorter time than the conventional charge pump. The propose analog switch CMOS charge pump shows compatible performance of the ideal diode or Dickson charge pump.

• The Journal of The Korea Institute of Intelligent Transport Systems
• /
• v.11 no.4
• /
• pp.63-69
• /
• 2012

This paper describes novel scheme of a gray scale capacitive fingerprint image for high-accuracy capacitive sensor chip. The typical gray scale image scheme used a DAC of big size layout or charge-pump circuit of non-volatile memory with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit of charge sharing scheme is proposed, which uses DLC(down literal circuit) based on a neuron MOS(vMOS) and analog simple multiplexor. The detection circuit is designed and simulated in 3.3V, $0.35{\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, a pixel layout size can be reduced and the image resolution can be improved.

• Journal of the Semiconductor & Display Technology
• /
• v.21 no.1
• /
• pp.50-55
• /
• 2022

Due to the wavelength shift problem of micro LED caused by the change of current density, the active matrix driving pixel circuit that is used in OLED cannot be applied to micro LED displays. Therefore, we need a gray scale method based on modulation of duration time of light emission. In this study, we propose the PWM-controlled micro LED pixel circuit based on CMOS thin film transistors (TFTs). By adopting CMOS inverter structure, we can reduce the number of storage capacitors from the circuit and make the operating speed of the circuit faster. Most of all, our circuit is designed to make operating speed of PWM circuit faster by adopting feedback effect through double gate TFT structure. As a result, it takes about 4.7ns to turn on the LED and about 5.6ns to turn it off. This operating time is short enough to avoid the color distortion and help the precise control of the gray scale.