• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.703-717
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• 2002

This paper illustrates the implementation of a scalable shared buffer asynchronous transfer mode (ATM) switch. The designed shared buffer ATM switch has a shared buffet of a pipelined memory which has the access time of 4 ns. The high-speed buffer access time supports a possibility of the implementation of a shared buffer ATM switch which has a large switching capacity. The designed switch architecture provides flexible switching performance and port size scalability with the independence of queue address control from buffer memory control. The switch size and the buffer size of the designed ATM switch can be reconfigured without serious circuit redesign. The designed prototype chip has a shared buffer of 128-cell and 4 ${\times}$ 4 switch size. It is integrated in 0.6um, double-metal, and single-poly CMOS technology. It has 80MHz operating frequency and supports 640Mbps per port.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.169-177
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• 2015

This paper proposes a hardware architecture for an efficient SAO(Sample Adaptive Offset) with low area for HEVC(High Efficiency Video Coding) encoder. SAO is a newly adopted technique in HEVC as part of the in-loop filter. SAO reduces mean sample distortion by adding offsets to reconstructed samples. The existing SAO requires a great deal of computational and processing time for UHD(Ultra High Definition) video due to sample by sample processing. To reduce SAO processing time, the proposed SAO hardware architecture processes four samples simultaneously, and is implemented with a 2-step pipelined architecture. In addition, to reduce hardware area, it has a single architecture for both luma and chroma components and also uses optimized and common operators. The proposed SAO hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 190k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 200MHz, it can support 4K UHD video encoding at 60fps in real time, but operates at a maximum of 250MHz.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.94-97
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• 2002

A VLSI architecture of an Ogg Vorbis decoder is proposed : which is dedicated to portable audio appliances. Referring to the computational cost analysis of the decoding processes, the LSP (Line Spectrum Pair) process, which takes more than 50% of the total processing time, can be regarded as a bottleneck to achieve realtime processing by embedded Processors. Thus in our decoder a specific hardware architecture is devised for the LSP process so as to be integrated into a single chip together with an ARM7TDMI processor. In addition, in order to reduce the total hardware cost, instead of the floating point arithmetic, the fixed point arithmetic is adopted. The LSP module has been implemented with 9,740 gates by using a Virtual Silicon 0.l5$\mu\textrm{m}$ CMOS technology, which operates at 58.8MHz with the total CPU load reduced by 57%. It is also verified that the use of the fixed point arithmetic does not incur any significant sound distortion.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.165-175
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• 2010

This paper presents a fine-grain supply-voltage-control scheme for low-power FPGAs. The proposed supply-voltage-control scheme detects the critical path in real time with small overheads by exploiting features of asynchronous architectures. In an FPGA based on the proposed supply-voltage-control scheme, logic blocks on the sub-critical path are autonomously switched to a lower supply voltage to reduce the power consumption without system performance degradation. Moreover, in order to reduce the overheads of level shifters used at the power domain interface, a look-up-table without level shifters is employed. Because of the small overheads of the proposed supply-voltage-control scheme and the power domain interface, the granularity size of the power domain in the proposed FPGA is as fine as a single four-input logic block. The proposed FPGA is fabricated using the e-Shuttle 65 nm CMOS process. Correct operation of the proposed FPGA on the test chip is confirmed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.193-202
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• 2010

This paper presents a high-speed low-complexity pipelined Reed-Solomon (RS) (255,239) decoder using pipelined reformulated inversionless Berlekamp-Massey (pRiBM) algorithm and its folded version (PF-RiBM). Also, this paper offers efficient pipelining and folding technique of the RS decoders. This architecture uses pipelined Galois-Field (GF) multipliers in the syndrome computation block, key equation solver (KES) block, Forney block, Chien search block and error correction block to enhance the clock frequency. A high-speed pipelined RS decoder based on the pRiBM algorithm and its folded version have been designed and implemented with 90-nm CMOS technology in a supply voltage of 1.1 V. The proposed RS(255,239) decoder operates at a clock frequency of 700 MHz using the pRiBM architecture and also operates at a clock frequency of 750 MHz using the PF-RiBM, respectively. The proposed architectures feature high clock frequency and low-complexity.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.12
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• pp.1878-1888
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• 1990

In this paper, the input-output interconnection method of the multi-valued signal processing circuit using perfect Shuffle technique and Kronecker product is discussed. Using this method, the design method of circuit of the multi-valued Reed-Muller expansions(MRME) to be used the multi-valued signal processing on finite field GF(p**m) is presented. The proposed input-output interconnection method is shown that the matrix transform is efficient and that the module structure is easy. The circuit design of MRME on FG(p**m) is realized following as` 1) contructing the baisc gates on GF(3) by CMOS T gate, 2) designing the basic cells to be implemented the transform and inverse transform matrix of MRME using these basic gates, 3) interconnecting these cells by the input-output interconnecting method of the multivalued signal processing circuits. Also, the circuit design of the multi-valued signal processing function on GF(3\ulcorner similar to Winograd algorithm of 3x3 array of DFT (discrete fourier transform) is realized by interconnection of Perfect Shuffle technique and Kronecker product. The presented multi-valued signal processing circuits that are simple and regular for wire routing and posses the properties of concurrency and modularity are suitable for VLSI.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.81-88
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• 2004

In this paper, a low power area efficient charge recycling predecoder (AE-CRPD) is proposed. The AE-CRPD is modified from the conventional charge recycling predecoder (CNV-CRPD). The AE-CRPD significantly reduces the area and power of the control circuits for the charge recycling operation. It saves 38% area and 8% power of the 2-to-4 CNV-CRPD. It also utilizes the property of the consecutive address increase in the memory. The AE-CRPDs are used for the frequently transited least significant bits and the conventional predecoders are used for the occasionally transited most significant bits. It saves 23% power of the 12-bit conventional predecoder.

• ETRI Journal
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• v.39 no.3
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• pp.326-335
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• 2017

In the uplink transmission of massive (or large-scale) multi-input multi-output (MIMO) systems, large dimensional signal detection and its hardware design are challenging issues owing to the high computational complexity. In this paper, we propose low-complexity hardware architectures of Richardson iterative method-based massive MIMO detectors. We present two types of massive MIMO detectors, directly mapped (type1) and reformulated (type2) Richardson iterative methods. In the proposed Richardson method (type2), the matrix-by-matrix multiplications are reformulated to matrix-vector multiplications, thus reducing the computational complexity from $O(U^2)$ to O(U). Both massive MIMO detectors are implemented using a 65 nm CMOS process and compared in terms of detection performance under different channel conditions (high-mobility and flat fading channels). The hardware implementation results confirm that the proposed type1 Richardson method-based detector demonstrates up to 50% power savings over the proposed type2 detector under a flat fading channel. The type2 detector indicates a 37% power savings compared to the type1 under a high-mobility channel.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.2000-2003
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• 2002

In this paper, an IC chip of a cell- network type circuit constructed with 1-dimensional chaos circuits is reported. The circuit, is designed by sing switched-current (Sl) techniques. In the proposed circuit, by controlling connections of cells, an S- dimensional circuit (S ＝ 1, 2, 3,…) and a synchronization system can be constructed easily. Furthermore, in spite of faults of a few cells, the circuit can reconstruct above-mentioned systems only to change connections of cells. This feature will open up new vista for engineering applications which are used in a distance place such as space, deep sea, etc. since it is difficult to repair faults of these application systems. To investigate the characteristics of the circuit, SPICE simulations are performed. The VLSI chip is fabricated from the layout design using a CAD tool, MAGIC. The proposed circuit is integrable by a standard 1.2 $\mu\textrm{m}$ CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.55-60
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• 2010

For battery-powered device applications, which grow rapidly in the electronic market today, low-power becomes one of the most important design issues of CMOS VLSI circuits. A multi-VDD system, which uses more than one power-supply voltage in the same system, is an effective way to reduce the power consumption without degrading operating speed. However, in the multi-VDD system, level converters should be inserted to prevent a large static current flow for the low-to-high conversion. The insertion of the level converters induces the overheads of power consumption, delay, and area. In this paper, we propose a new level converter which can provide the level up/down conversions for the various input and output voltages. Since the proposed level converter uses only one power-supply voltage, it has an advantage of reducing the complexity in physical design. In addition, the proposed level converter provides lower power and higher speed, compared to existing level converters.