• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.1
• /
• pp.45-50
• /
• 2007

This paper proposes a low power selective data write (SDW) scheme for a phase-change random access memory (PRAM). The PRAM consumes large write power because large write currents are required during long time. At first, the SDW scheme reads a stored data during write operation. And then, it writes an input data only when the input and stored data are different. Therefore, it can reduce the write power consumption to a half. The 1K-bit PRAM test chip with $128{\times}8bits$ is implemented with a $0.8{\mu}m$ CMOS technology with a $0.8{\mu}m$ GST cell.

• Proceedings of the IEEK Conference
• /
• 2001.06a
• /
• pp.155-158
• /
• 2001

A 640Gb/s high-speed ATM switching system that is based on the technologies of advanced MCM, 0.25um CMOS and optical WDM interconnection is fabricated for future N-ISDN services. A 40 layer, 160mm$\times$114mm ceramic MCM realizes the basic ATM switch module with 80Gbps throughput. The basic unit ATM switch module with 80Gb/s throughput. The basic unit ATM switch MCM consists of in 8 chip advanced 0.25um CMOS VLSI and 32 chip I/O Bipolar VLSIs. The MCM employs an 40 layer, very thin layer ceramic MCM and a uniquely structured closed loop type liquid colling system is adopted to cope with the MCM's high-power dissipation of 230w. The MCM is Mounted on a 32cm$\times$50cm mother board. A three stage ATM switch is realized by optical WDM interconnection between the high-performance MCM.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2001.10a
• /
• pp.648-651
• /
• 2001

This paper describes the 8-error-correction (204, 188) Reed-Solomon Decode. over GF(2$^{8}$ ) for a satellite communication. It is synthsized using a CMOS library. Decoding algorithm of Reed-Solomon codes consists of four steps which are to compute syndromes, to find error-location polynomial, to decide error-location, and to slove error-values. The decoder is designed using Modified Euclid algorithm in this paper. First of all, The functionalities of the circuit are verified through C++ programs, and then it is designed in Verilog HDL. It is verified through the logic simulations of each blocks. Finally, The Reed-Solomon Decoder is synthesized with Synopsys Tool.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.3
• /
• pp.531-536
• /
• 2009

In this paper, we propose $256{\times}256$ pixel array fingerprint sensor with an advanced circuits for detecting. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. We minimizes an electrostatic discharge(ESD) influence by applying an effective isolation structure around the unit pixel. The sensor circuit blocks were designed and simulated in standard CMOS $0.35{\mu}m$ process. Full custom layout is performed in the unit sensor pixel and auto placement and routing is performed in the full chip.

• The KIPS Transactions:PartA
• /
• v.11A no.2
• /
• pp.115-122
• /
• 2004

In this paper, the multiple-valued adders and multipliers are implemented by current-mode CMOS. First, we implement the 3-valued T-gate and the 4-valued T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second we implement the circuits to be realized 2-variable 3-valued addition table and multiplication table over finite fields $GF(3^2)$, and 2-variable 4-valued addition table and multiplication table over finite fields $GF(4^2)$ with the multiple-valued T-gates. Finally, these operation circuits are simulated under $1.5\mutextrm{m}$ CMOS standard technology, $15\mutextrm{A}$ unit current, and 3.3V VDD voltage Spice. The simulation results have shown the satisfying current characteristics. The 3-valued adder and multiplier, and the 4-valued adder and multiplier implemented by current-mode CMOS is simple and regular for wire routing and possesses the property of modularity with cell array. Also, since it is expansible for the addition and multiplication of two polynomials in the finite field with very large m, it is suitable for VLSI implementation.

• IT SoC Magazine
• /
• s.3
• /
• pp.35-37
• /
• 2004

본 연구팀이 Hynix 0.35um CMOS 4M 2P 공정을 사용하여 제작한 민수용 DDFS (DAC를 포함한 single chip)는 DC부터 100MHz 까지 사용할 수 있으며(BW=100MHz) frequency 변환속도 약 30nS, 주파수해상도 0.0745Hz, 그리고 소비 전력은 120MHz 클럭에서 약 200mW이다. 본고에서는 언급하지 않았지만, 본 연구팀이 별도의 설계로 진행된 군수용 DDFS의 경우, 출력주파수는 DC부터 320MHz 까지 가능하고 소비 전력은 800MHz 클럭에서 약 400mW이다. 이처럼 DDFS는 특성 자체의 우수성 뿐 아니라, 각종 멀티미디어 기기 및 통신시스템의 급격한 디지털화 추세로 인해 주파수합성기도 디지털화 함으로써 VLSI화가 용이하고, 이에 따라 S/W에 의한 다기능화 (programmability), 응용성의 극대화, 및 저가격화를 추구할 수 있다는 점에서 주목해야 할 분야이다. 특히 반도체기술의 발전으로 지금까지 DDFS 구현의 가장 큰 장애로 대두되던 DAC의 고속화가 부분적으로 가능해지면서 (TTL-to-ECL interface 부가회로가 별도로 필요없이 직접적인 연결), DDFS의 시장 전망을 더욱 밝게 하고 있다.

• Proceedings of the IEEK Conference
• /
• 2002.07a
• /
• pp.313-316
• /
• 2002

This paper presents the design and implementation of a crypto processor, a special-purpose microprocessor optimized for the execution of cryptography algorithms. This crypto processor can be used fur various security applications such as storage devices, embedded systems, network routers, etc. The crypto processor consists of a 32-bit RISC processor block and a coprocessor block dedicated to the SEED and triple-DES (data encryption standard) symmetric key crypto (cryptography) algorithms. The crypto processor has been designed and fabricated as a single VLSI chip using 0.5 $\mu\textrm{m}$ CMOS technology. To test and demonstrate the capabilities of this chip, a custom board providing real-time data security for a data storage device has been developed. Testing results show that the crypto processor operates correctly at a working frequency of 30MHz and a bandwidth o1240Mbps.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.5 no.4
• /
• pp.443-449
• /
• 2010

Current testing is an effective method which offers higher fault detection and diagnosis capabilities than voltage testing. Since current testing requires much longer testing time than voltage testing, it is important to note that a fault is untestable if the two nodes have same values at all times. In this paper, we present an object oriented fault detection scheme for various fault models using current testing. Experimental results for ISCAS benchmark circuits show the effectiveness of the proposed method in reducing the number of faults and its usefulness in various fault models.

• Proceedings of the KIEE Conference
• /
• 2003.11b
• /
• pp.67-70
• /
• 2003

In this paper the main topologies of one-bit full adders, including the most interesting of those recently proposed, are analyzed and compared for speed, power consumption, and power-delay product. The comparison has been performed on circuits, optimized transistor dimension to minimize power-delay product. The investigation has been carried out with properly defined simulation runs on a Cadence environment using a 0.25-${\mu}m$ process, also including the parasitics derived from layout. Performance has been also compared for different supply voltage values. Thus design guidelines have been derived to select the most suitable topology for the design features required. This paper also proposes a novel figure of merit to realistically compare n-bit adders implemented as a chain of one-bit full adders. The results differ from those previously published both for the more realistic simulations carried out and the more appropriate figure of merit used. They show that, except for short chains of blocks or for cases where minimum power consumption is desired, topologies with only pass transistors or transmission gates are not attractive.

• Journal of information and communication convergence engineering
• /
• v.7 no.1
• /
• pp.66-71
• /
• 2009

A novel sensing scheme using resistive characteristics of the finger is proposed. ESD problem is more harmful than a capacitive fingerprint sensor in a resistive fingerprint sensor, because the sensor plate is directly connected to the sensing cell. The proposed circuit is more robust than conventional circuit for ESD. The sensor plate and sensing cell are isolated by capacitor. The pixel level simple detection circuit is fully digital operation unlike that of the capacitive sensing cell. The sensor circuit blocks are designed and simulated in a standard CMOS $0.35{\mu}m$ process. The proposed circuit is more stable and effective than a typical circuit.