• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5A
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• pp.497-502
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• 2007

Broadband monolithic SiGe HBT variable gain amplifier with a feedforward configuration have been newly developed to improve bandwidth and dB-linearly controlled gain characteristics. The VGA has been implemented in a $0.35-{\mu}m$ BiCMOS process. The VGA achieves a dynamic gain-control range of 19.6 dB and a 3-dB bandwidth of 4 GHz ($4{\sim}8\;GHz$) with the control-voltage range from 0.6 to 2.6 V. The VGA produces a maximum gain of 9.3 dB at 6 GHz and a output power of -3 dBm at 8 GHz.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.4 s.316
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• pp.27-34
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• 2007

In this paper device driver for camera capture in hand held mobile system is implemented based on microsoft windows CE operating system. We also study the storage device driver based on the FAT fie system by using NAND flash memory as a storage device. We use the MBA2440 PDA board for implementing the hardware for image capture by using CMOS camera module producted by PixelPlus company. This camera module has VGA $640{\times}480$ pixel resolution. We also make application program which can be cooperated with the device driver for testing its performance, for example image capture speed and quality of captured image. We check that the application can be cooperated well not only with the device driver for camera capture but also with the device driver for FAT file system designed especially for the NAND flash memory.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.31-39
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• 2011

In this paper, we propose a signal readout system with small area and low power consumption for CNT sensor arrays. The proposed system consists of signal readout circuitry, a digital controller, and UART I/O. The key components of the signal readout circuitry are 64 transimpedance amplifiers (TIA) and SAR-ADC with 11-bit resolution. The TIA adopts an active input current mirror (AICM) for voltage biasing and current amplification of a sensor. The proposed architecture can reduce area and power without sampling rate degradation because the 64 TIAs share a variable gain amplifier (VGA) which needs large area and high power due to resistive feedback. In addition, the SAR-ADC is designed for low power with modified algorithm where the operation of the lower bits can be skipped according to an input voltage level. The operation of ADC is controlled by a digital controller based on UART protocol. The data of ADC can be monitored on a computer terminal. The signal readout circuitry was designed with 0.13${\mu}m$ CMOS technology. It occupies the area of 0.173 $mm^2$ and consumes 77.06${\mu}W$ at the conversion rate of 640 samples/s. According to measurement, the linearity error is under 5.3% in the input sensing current range of 10nA - 10${\mu}A$. The UART I/O and the digital controller were designed with 0.18${\mu}m$ CMOS technology and their area is 0.251 $mm^2$.

• 한국ITS학회:학술대회논문집
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• 2008.11a
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• pp.380-382
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• 2008

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.22-28
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• 2009

This paper presents a fast received signal strength indicator (RSSI) circuit for wireless communication application. The proposed circuit is developed using power detectors and an analog-to-digital converter to achieve a fast settling time. The power detector is consisted of a novel logarithmic variable gain amplifier (VGA), a peak detector, and a comparator in a closed loop. The VGA achieved a wide logarithmic gain range in a closed loop form for stable operation. For the peak detector, a fast settling time and small ripple are obtained using the orthogonal characteristics of quadrature signals. In $0.18-{\mu}m$ CMOS process, the RSSI value settles down in $20{\mu}s$ with power consumption of 20 mW, and the maximum ripple of the RSSI is 30 mV. The proposed RSSI circuit is fabricated with a personal handy-phone system transceiver. The active area is $0.8{\times}0.2\;mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.277-282
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• 2008

A fully integrated inductorless CMOS impulse radio ultra-wideband (IR-UWB) receiver is implemented using $0.18\;{\mu}m$ CMOS technology for 3-5 GHz application. The UWB receiver adopts the non-coherent architecture, which removes the complexity of RF architecture and reduces power consumption. The receiver consists of inductorless differential three stage LNA, envelope detector, variable gain amplifier (VGA), and comparator. The measured sensitivity is -70 dBm in the condition of 5 Mbps and BER of $10^{-3}$. The receiver chip size is only $1.8\;mm\;{\times}\;0.9\;mm$. The consumed current is 15 mA with 1.8 V supply.

• Proceedings of the IEEK Conference
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• summer
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• pp.221-224
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• 2004

This paper proposed an ultra low-power CMOS exponential voltage-mode circuit using the Pseudo-exponential function for realizing the exponential characteristics. The proposed circuit provides high dB-linear output voltage range at low-voltage applications. In a $0.25\;\mu m$ CMOS process, the simulations show more than 35 dB output voltage range and 26 dB with the linearity error less than $\pm0.5\;dB.$ The average current consumption is less than 80 uA. The proposed circuit can be used for the design of an extremely low-power variable gain amplifier (VGA) and automatic gain control (AGC).

• ETRI Journal
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• v.26 no.5
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• pp.486-492
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• 2004

The emergence of wide channel bandwidth wireless standards requires the use of a highly linear, wideband integrated CMOS baseband chain with moderate power consumption. In this paper, we present the design of highly linear, wideband active RC filters and a digitally programmable variable gain amplifier. To achieve a high unity gain bandwidth product with moderate power consumption, the feed-forward compensation technique is applied for the design of wideband active RC filters. Measured results from a $0.5{\mu}m$ CMOS prototype baseband chain show a cutoff frequency of 10 MHz, a variable gain range of 33 dB, an in-band IIP3 of 13 dBV, and an input referred noise of 114 ${\mu}Vrms$ while dissipating 20 mW from a 3 V supply.

• ETRI Journal
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• v.29 no.4
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• pp.421-429
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• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

• Journal of Information Display
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• v.3 no.2
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• pp.1-5
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• 2002

A CMOS driving circuit for active matrix type polymer electroluminescent displays was designed to develop an on-chip microdisplay on the single crystal silicon wafer substrate. The driving circuit is a conventional structure that is composed of the row, column and pixel driving parts. 256 gray scales were implemented using pulse amplitude modulation method. The 2-transistor driving scheme was adopted for the pixel driving part. The layout was carried out considering the compatibility with the standard CMOS process. Judging from the layout of the driving circuit, it turns that it is possible to implement a high-resolution display about 400 ppi resolution. Through the HSPICE simulation, it was verified that this circuit is capable of driving a VGA signal mode display and implementing 256 gray levels.