• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1055-1061
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• 2002

Conventional TSPC D flip-flop has the advantages of high speed, simple clock distribution, and no racing because of the single phase clocking strategy and its simple structure. But, it suffers from glitch, clock slope sensitivity and unbalanced propagation delay problems. Therefore, a new dynamic D flip-flop, which improves these disadvantages, is proposed. The main idea of this paper is DS(Discharge Suppression) scheme, which suppresses unnecessary discharge. As a result, the proposed structure is free from glitch problem and it improves maximum clock slope immunity from 0.25ns to Ins. Also, it uses only 8 transistors and it Is demonstrated that high speed operation is feasible by balancing propagation delay time.