• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6B
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• pp.1183-1190
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• 1999

This paper presents an efficient hardware architecture to improve the frame memory interface occupying the largest hardware area together with motion estimator in implementing MPEG-2 video encoder as an ASIC chip. In this architecture, the memory size for internal data buffering and hardware area for frame memory interface control logic are reduced through the efficient memory map organization of the external SDRAM having dual bank and memory access timing optimization between the video encoder and external SDRAM. In this design, 0.5 m, CMOS, TLM (Triple Layer Metal) standard cells are used as design libraries and VHDL simulator and logic synthesis tools are used for hardware design add verification. The hardware emulator modeled by C-language is exploited for various test vector generation and functional verification. The architecture of the improved frame memory interface occupies about 58% less hardware area than the existing architecture[2-3], and it results in the total hardware area reduction up to 24.3%. Thus, the (act that the frame memory interface influences on the whole area of the video encoder severely is presented as a result.

• The Transactions of the Korea Information Processing Society
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• v.5 no.6
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• pp.1620-1632
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• 1998

This paper presents a fast parallel algorithm for volume rendering and its implementation using C language and MPI MasPar Programming Language) on the 4,096 processor MasPar MP-2 machine. This parallel algorithm is a parallelization hased on the Lacroute' s sequential shear - warp algorithm currently acknowledged to be the fastest sequential volume rendering algorithm. This algorithm reduces communication overheads by using the sheared space partition scheme and the load balancing technique using load estimates from the previous iteration, and the number of voxels to be processed by using the run-length encoded volume data structure.Actual performance is 3 to 4 frames/second on the human hrain scan dataset of $128\times128\times128$ voxels. Because of the scalability of this algorithm, performance of ]2-16 frames/sc.'cond is expected on the 16,384 processor MasPar MP-2 machine. It is expected that implementation on more current SIMD or MIMD architectures would provide 3O~60 frames/second on large volumes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.3
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• pp.55-61
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• 2000

This paper presents an efficient hardware architecture of frame memory interface in MPEG-2 video encoder. To reduce the size of memory buffers between SDRAM and the frame memory module, the number of clocks needed for each memory access is minimized with dual bank operation and burst length change. By allocating the remaining cycles not used by SDRAM access, to the random access cycle, the internal buffer size, the data bus width, and the size of the control logic can be minimized. The proposed architecture is operated with 54MHz clock and designed with the VT $I^{тм}$ 0.5 ${\mu}{\textrm}{m}$ CMOS TLM standard cell library. It is verified by comparing the test vectors generated by the c-code model with the simulation results of the synthesized circuit. The buffer area of the proposed architecture is reduced to 40 % of the existing architecture.

• Journal of Internet Computing and Services
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• v.11 no.4
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• pp.119-128
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• 2010

Computing environment in these days aim for user-oriented development called RIA (Rich Internet Application). As a representative development method of RIA, Flex Framework overcomes the weaknesses of the Mainframe and C/S (Client/Server). However, the issues, such as, difficulties in memory management, complexity of the binding structure and large capacities of the compile outputs are left to be solved. The purpose of this paper is to implement the framework which enables the fast and accurate development of user-oriented web application on the Flex platform. DDX (Dynamic Data eXchange) framework proposes standardized and efficient development environment in a Flex platform. And by using scalability-prepared library that is applicable for various job areas, the framework enhances the performance, increase development productivity and help construct stable system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.10
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• pp.1889-1899
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• 2015

In this paper, we propose a multiple slot reservation scheme to transmit data rapidly in the satellite random access channel. In the R-CRDSA (Reservation scheme with Contention Resolution Diversity Slotted ALOHA), each satellite terminal can use only one slot in a frame. Therefore, many slots are wasting in the low traffic load and the satellite terminals which have large date needs many frame to transmit their data although there are unused slots. In the multiple slot reservation scheme, each satellite terminal transmits a packet with their data size and reserves many slots in the light of data size and slot reservation status. Therefore, each satellite terminal transmits their data faster than R-CRDSA. This is because they can reserve many slots in a frame. Furthermore, we simulate proposed scheme and validate the performance of proposed scheme.

• 한국경영정보학회:학술대회논문집
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• 2007.11a
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• pp.309-315
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• 2007

SK텔레콤은 급변하는 이동통신시장 환경의 변화에 적절히 대응하기 위하여 지난 10여 년간 사용해 온 메인프레임 기반의 COIS 시스템을 중단하고 Unix 기반의 NGM 시스템으로 다운사이징하기로 결정하였다. 2002 년 9 월 SK 텔레콤은 차세대 IT 인프라 혁신 전략 프로젝트를 완료하고 이에 근거하여 2003 년 말 1 단계 프로젝트를 추진하게 된다. 그러나 개발 툴의 문제점, Governance 의 확보 실패 등 문제점이 계속 누적되어 2005년에 접어들어서는 총체적 난국 상황에 봉착하게 되었다. 2005 년 2 월 자체 점검 결과 개발 진척도는 50%에 불과한 상황이었다. 결국 2005 년 3 월, NGM 추진본부는 프로젝트의 추진 중단을 선언하기에 이르렀다. NGM 프로젝트는 처음부터 재 검토하여 Re-planning 을 실시한 후 구축을 재개하기로 결정하였다. 2005 년 5 월 NGM 프로젝트의 Re-plan 이 수립되었다. 우선 Turn-key 방식의 문제점을 해소하기 위하여 SK 텔레콤이 구축의 총책임을 떠맡고, SK C&C 가 시스템 이행에 대한 책임을 지는 Governance 체제를 확립하였다. 또한 2 단계 프로젝트에서는 NGM 프로젝트를 기술적으로 원점부터 재 검토하여 이전과는 근본적으로 다른 In-House 구축 접근방식을 채택하기로 하였다. 2 단계 프로젝트에서 관심을 집중한 기술적 의사결정 영역은 크게 (1) 미들웨어 및 개발프레임워크의 적용, (2) DB 아키텍처의 결정 및 슬림화, (3) 시스템 성능 개선 등의 세 분야로 집약할 수 있다. 이 논문에서는 이들 각각의 분야를 구체적으로 검토하였다. 결국 2006 년 10 월 9 일 메인프레임 기반의 COIS 는 Shut-down 되어 가동을 멈추었고, Unix 기반의 NGM 시스템이 가동을 개시함으로써 차세대 마케팅을 본격 추진하기 위한 다운사이징 프로젝트가 성공적으로 완수되었다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.56-65
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• 1999

This paper presents an architecture and its instruction set for a graphic coprocessor(GCP) which can be used for a multimedia server. The proposed instruction set employs parallel architecture concepts, such as SIMD and Superscalar. GCP consists of a scheduler and four functional units. The scheduler solves an instruction bottleneck problem causing by sharing with four general processors(GPs). GCP can execute up to 4 instructions in parallel. It consists of about 56,000 gates and operates at 30 MHz clock frequency due to speed limitation of SOG technology. GCP meets the real-time DCT algorithm requirement of the CIF image format and can process up to 63 frames/sec for the DCT Algorithm and 21 frames/sec for the Full Block matching Algorithm of the CIF image format.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.29 no.6
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• pp.276-282
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• 2019

The purpose of this study was to analyze the structure of general filter using ultrafine filter (Profilter), dust collector filter, HEPA (HAPA-High Efficiency Particulate Air) filter, deodorized filters, etc. of air purifiers and to study new types of purified filters that can improve ultrafine dust, harmful gases, and sterilization cleanup performance. The study was also conducted by adding photocatalyst filters to the existing step-by-step filtration filter types, which were proposed in the design three coupling structure filters of the left and right UV-LED installation frames and the photocatalyst coating honeycomb frame. Future research is needed on the effect of photocatalyst filters. This study was to investigate the application and structure of photocatalyst filters to air purifiers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.445-453
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• 2002

We propose a cell-multiplexing scheme for the real-time communication service in ATM network and a new service discipline guarantee end-to-end delay based on pseudo-isochronous cell switching. The proposed scheme consists of two level frame hierarchy, upper and lower frame, which is used to assign the bandwidth and to guarantee the requested delay bound, respectively. Since the proposed algorithm employs two level frame hierarchy, it can overcome the coupling problem which is inherent to the framing strategy. The proposed scheme consists of two components, traffic controller and scheduller, as the imput traffic description model and regulates the input traffic specification. The function of the traffic controller is to shape real-time traffic to have the same input pattern at every switch along the path. The end-to-end delay is bounded by the scheduller which can limit the delay variation without using per-session jitter controllers, and therefore it can decrease the required buffer size. The proposed algorithm can support the QoS's of non-real time traffic as well as those of real time traffic

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.486-495
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• 2002

In this paper, we propose a delay reduction method for frame-based packet transmit scheduling algorithm. A high-speed network such as ATM network has to provide some performance guarantees such as bandwidth and delay bound. Framing strategy naturally guarantees bandwidth and enables simple rate-control while having the inherently bad delay characteristics. The proposed delay reduction method uses the same hierarchical frame structure as HRR (Hierarchical Round-Robin) but does not use the static priority scheme such as round-robin. Instead, we use a dynamic priority change scheme so that the delay unfairness between wide bandwidth connection and narrow bandwidth connection can be eliminated. That is, we use FIFO (First-In First-Out) concept to effectively reduce the occurrence of worst-case delay and to enhance delay distribution. We compare the performance for the proposed algorithm with that of HRR. The analytic and simulation results show that HFIFO inherits almost all merits of HRR with fairly better delay characteristics.