• 한국ITS학회:학술대회논문집
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• v.2006 no.10
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• pp.166-170
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• 2006

• Transportation Technology and Policy
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• v.10 no.3
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• pp.6-13
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• 2013

• Journal of Electrical Engineering and Technology
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• v.4 no.4
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• pp.429-437
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• 2009

This paper proposes a hybrid voltage controller based on a hierarchical control structure for implementation in the Jeju power system. The hybrid voltage controller utilizes the coordination of various reactive power devices such as generators, switched shunt devices and LTC to regulate the pilot voltage of an area or zone. The reactive power source can be classified into two groups based on action characteristics, namely continuous and discrete. The controller, which regulates the pilot bus voltage, reflects these characteristics in the coordination of the two types of reactive power source. However, the continuous type source like generators is a more important source than the discrete type for an emergency state such as a voltage collapse, thereby requiring a more reactive power reserve of the continuous type to be utilized in the coordination in order to regulate the pilot bus voltage. Results show that the hybrid controller, when compared to conventional methods, has a considerable improvement in performance when adopted to control the pilot bus voltage of the Jeju island system.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.3
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• pp.82-87
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• 2007

This paper measures power quality of bus in case electric charges about customer are imposed by each bus, supposed that can calculate this cost. When reflected this in system planning, expected cost proposed following method through sample system. To calculate nodal cost operating condition of power equipment calculates nodal cost[$/MVAH] supposing by situation that is optimized by OPF(optimal power flow) in system. The damage cost that is shed by fault that happen during year of loads in system that is linked on each bus was produced. As a result, proposed method was very effective in case of calculating bus total cost including power quality cost.

• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.1
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• pp.1-8
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• 2018

A problem exists in the conventional transportation cart applications, in which an external power supply with mechanical contact connection (bus bar connection) is required to drive the motor. Therefore, continuous effort for maintenance is required, aside from the expensive bus bar connector. To solve this problem, a self-electricity-generated transportation cart system without bus bar has recently been introduced. In this system, a battery needs to store the power of the generated wheel, and a boost converter, which converts the low battery voltage to high bus voltage to drive the motor inverter, is necessary. However, since the instantaneous large current required for starting the motor is supplied from the battery, a battery with large size and volume should be adopted to withstand this large current. In this study, a boost converter that can supply a large instantaneous current by using super Capacitor string is proposed. The proposed converter can be realized with a small size and volume compared with the conventional battery-fed boost converter. Operational principles, analysis, and design of the proposed converter are presented, and experimental results are provided to validate the proposed converter.

• Journal of information and communication convergence engineering
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• v.9 no.4
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• pp.428-430
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• 2011

Recent semiconductor design technology has been substantially developed that we can design a micro-system on a chip as well as implementing an application specific IC in an FPGA. SPARTAN-3E developed by Xilinx is equipped with an FPGA that holds as much as 500 thousand transistors connected with MicroBlaze softcore microprocessor bus system. In this paper, we discuss a method of implementing an embedded system using the SPARTAN-3E. We also explain the peripherals and the bus protocols and the expandability of this kind of embedded systems.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.12 no.4
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• pp.1-10
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• 2013

This study was conducted to investigate that bus information was used as an information of travel speed. To determine the travel speed on the road, bus information and the information collected from the point detector and the interval detection installed were compared. If bus information has the function of traffic information detector, can provide the travel speed information to road users. To this end, the model of recognizing the traffic patterns is necessary. This study used simple moving-average method, simple exponential smoothing method, Double moving average method, Double exponential smoothing method, ARIMA(Autoregressive integrated moving average model) as the existing methods rather than new approach methods. This study suggested the possibility to replace bus information system into other information collection system.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.44 no.9
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• pp.825-832
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• 2016

This paper describes the development of a data bus analyzer for use in avionics systems integration test. The data bus analyzer is equipped with MIL-STD-1553B, CAN and Ethernet interface cards which is incorporated in a majority of the avionics systems to accommodate a variety of interfaces. It has an individual hardware for a capture engine and a analyzing engine in order to perform the collection and the analysis of the bus data at the same time efficiently. It provides a data display function of the grid, 2-dimensional and 3-dimensional form to increase the data analysis efficiency. Verification of the data bus analyzer was carried out module unit testing and inter-module integration testing on the basis of the test procedures. Verification of interlocking requirement and usefulness of developed equipment was confirmed through an integration test result performed on a system integration laboratory of aircraft which is an actual testing environment.

• The Journal of the Korea Contents Association
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• v.19 no.2
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• pp.349-367
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• 2019

This paper empirically analyzed the factors of operational efficiency after the quasi-public bus operating system in Busan Metropolitan City. DEA analysis result, for CRS the annual efficiency in 2010 of bus routes that can be transferred to subway lines 1 was the highest. The annual efficiency of bus routes that can be transferred to subway lines 2 shows the largest annual average of 0.923 in 2016 under the CRS average gradually improved over the year. Annual efficiency of subway lines No. 3 and transferable bus routes gradually improved from 2009 to 2015, but declined again in 2016. Among 536 routes for four years on 134 routes per year, 205 routes were found to be inefficient. In order to increase efficiency of the 205 routes, it is suggested that the number of routes should be reduced. In addition, the analysis results on DEA using the Tobit calibration, the most significant factors affecting the operational efficiency index were the time taken, followed by the number of passengers and the number of passengers transferred.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.224-240
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• 1996

It is common sense for at least one or more levels of cache memory to be used in these day's computer systems. In this paper, the impact of the internal cache memory organization on the performance of the computer is investigated by using a simulator program, which is wirtten by authors and run on SUN SPARC workstation, with several real execution, with several real execution trace files. 280 cache organizations have been simulated using n-way set associative mapping and LRU(Least Recently Used) replacement algorithm with write allocation policy. As a result, 16-way setassociative cache is the best configuration, and when we select 256KB cache memory and 64 byte line size, the bus traffic ratio was decreased compared to that of the noncache system so that a single bus could support almost 7 processors without any delay and degradationof high ratio(hit ratio was 99.21%). The smaller the line size we choose, the little lower hit ratio we can get, but the more processors can be supported by a single bus(maximum 18 processors). Therefore, using a proper cache memory organization can make a single bus structure be able to support multiple processors without any performance degradation.