• 한국정보통신설비학회:학술대회논문집
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• 2009.08a
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• pp.138-140
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• 2009

This paper investigates a method to remove the undesirable resonance of the rectangular power-bus structure(PBS) using an inductive layer. The equivalent surface impedance of the proposed loading is calculated for characterizing the proposed EBG geometry. The effects of the strips and the immediate surroundings are illustrated by a number of numerical experiments.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.39 no.4
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• pp.333-340
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• 1990

분산 송전송실정보에 의한 전력시스템의 경제운용=The transmission loss information produced in a line may be shared by both end buses connected to the line. Then, the loss may be seen as if it is discretely produced at both buses. Likewise, all transmission losses can be considered as if they are discretely produced at every bus distributed. The bus transmission loss equation can be defined, in which the loss information about connected lines are contained. This formulation can greatly enhance the computational efficiency for the economic control of both real powers and voltages. It requires solutions of two linear matrix equations, one for the calculation of incremental transmission losses and the other for the determination of voltage levels to be controlled. The Proposed approach is demonstrated through three sample systems and it is found that the solutions can be obtained after three iterations regardless of system sizes. This implies that only one-step search would be required for the solution if real informations would be available. Results are compared with those of optimal power flows.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.35-44
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• 2005

SoC(systnn-on-a-chip) requires high bandwidth system bus for performing multiple functions. Performance of the system is affected by bandwidth of the system bus. In this paper, for efficient management of the bus resource on a SoC platform, we present a latency model of the shared bus organized by multiple layers. Using the latency model, we can analyze latencies of the shared bus on a SoC. Moreover we evaluate a throughput of the bus and compare with needed throughput of the SoC platform including IPs such as MPEG or USB 2.0. And we can use the results as a criteria to find out an optimal bus architecture for the specific SoC design. For verifying accuracy of the proposed model, we compared the latencies with the simulation result from MaxSim tools. As the result of simulation, the accuracy of the IS model for a single layer and multiple layer are over $96\%\;and\;85\%$ respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.69-78
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• 2010

To implement the high performance SoC, we propose the flying master bus architecture that a specially defined master named as the flying master directly accesses the selected slaves with no regard to the bus protocol. The proposed bus architecture was implemented through Verilog and mapped the design into Hynix 0.18um technology. As master and slave wrappers have around 150 logic gate counts, the area overhead is still small considering the typical area of modules in SoC designs. In TLM performance simulation about proposed architecture, 25~40% of transaction cycle and 43~60% of bus efficiency are increased and 43~77% of request cycle is decreased, compared with conventional bus architecture. Conclusively, we assume that the proposed flying master bus architecture is promising as the leading candidate of the bus architecture in the aspect of performance and efficiency.

• Journal of Korean Society of Transportation
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• v.33 no.6
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• pp.543-553
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• 2015

This study analyzed that the impact of the bus use environment on users' stress in each step of bus use, from accessing to leaving to transfer, in the city of Daejeon. For this, we collected the stress data from 300 users using personal interviews at the bus stops and on-board bus. Also, we used factor analysis and structural equation model method for analysis of the impact of external and internal bus environments on stress of users. The results of this study showed that the highest stress impact factor was an onboard factor(${\beta}=.416$) including 'density and crowding', 'no seat to seat' and 'low ride comfort and safe'. The next stress impact factor was transfer factor including 'insufficient transfer information', 'lack of connectivity of bus and subway' and 'uncomfort transfer route'. From the above, we recommend that bus policies need to focus on not the supplier but users and also, this user based policy need to be more specified considering the characteristics of various users such as females, the elderly, irregular users, and so on.

• Journal of the Economic Geographical Society of Korea
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• v.18 no.4
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• pp.539-555
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• 2015

This study proposes the methodology for measuring the time-distance accessibility on the Seoul bus system based on the T-card transaction databases and analyzes the results. T-card transaction databases contain the time/space information of each passenger's locations and times of the departure, transfers, and destination. We introduce the bus network graph and develop the algorithms for time-distance accessibility measurement. We account the average speed based on each passenger's get-in and getoff information in the T-card data as well as the average transfer time from the trip chain transactions. Employing the modified Floyd APSP algorithm, the shortest time distance between each pair of bus stops has been accounted. The graph-theoretic nodal accessibility has been given by the sum of the inverse time distance to all other nodes on the network. The results and spatial patterns are analyzed. This study is the first attempt to measure the time-distance accessibility for such a large transport network as the Seoul bus system consists of 34,934 bus stops on the 600 bus routes, and each bus route can have different properties in terms of speed limit, number of lanes, and traffic signal systems, and thus has great significance in the accessibility measurement studies.

• Information and Communications Magazine
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• v.14 no.12
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• pp.49-62
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• 1997

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.629-638
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• 2005

In the System on a Chip design, the on chip bus is one of the critical factors that decides the overall system performance. Especially, in the case or reusing the IPs such as processors, DSPs and multimedia IPs that requires higher bandwidth, the bandwidth problems of on chip bus are getting more serious. Recently ARM proposes the Multi-Layer AHB BusMatrix that is a highly efficient on chip bus to solve the bandwidth problems. The Multi-Layer AHB BusMatrix allows parallel access paths between multiple masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. However, there is one clock cycle delay for each master in existing Multi-Layer AHB BusMatrix whenever the master starts new transactions or changes the slave layers because of the Input Stage and arbitration logic realized with Moore type. In this paper, we improved the existing Multi-Layer AHB BusMatrix architecture to solve the one clock cycle delay problems and to reduce the area overhead of the Input Stage. With the elimination of the Input Stage and some restrictions on the arbitration scheme, we tan take away the one clock cycle delay and reduce the area overhead. Experimental results show that the end time of total bus transaction and the average latency time of improved Multi-Layer AHB BusMatrix are improved by $20\%\;and\;24\%$ respectively. in ease of executing a number of transactions by 4-beat incrementing burst type. Besides the total area and the clock period are reduced by $22\%\;and\;29\%$ respectively, compared with existing Multi-layer AHB BusMatrix.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.18 no.2
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• pp.1-11
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• 2019

The accident of mass transit such as a bus could draw the large casualties and this induces social and economic losses. Recently, severe bus accidents caused by tiredness and inattention of bus drivers occurred and those lead to growing interest in bus accidents and the drivers' work environment. Therefore, this study analyzes the accident based on the work environment of bus drivers and route-bus categories. For the research, this study collected digital tachograph data and the bus company information for 271 domestic bus companies in 2017 and used ANOVA test and chi-square test as statistical methodologies. As a result, we figured out there are statistically significant differences in the accident according to the working environments. Especially, the present study confirmed the intracity bus with working every other day has the most frequent accidents. We expect that the results of this study be used as foundations for the improvement of working conditions to reduce route-bus accidents in the future.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.26-32
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• 2008

The conventional shared bus architecture is capable of processing only one data transaction in same time. In this paper, we propose the NAWM (No Arbitration Wild Master) bus architecture that is capable of processing several data transactions in same time. After designing the master and the slave wrappers of NAWM bus architecture about AMBA system, we confirm that most of IPs of AMBA system can be a lied without modification and the added timing delay can be neglected. from simulation we deduce that more than 50% parallel processing is possible when several masters initiate slaves in NAWM bus architecture.