• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.2
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• pp.126-136
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• 2003

We propose a new technique to improve the parametric fault coverage of oscillation test method (OTM). The OTM has been popular as a vectorless scheme for analog circuit test, both as a general defect-oriented technique, as well as an oscillation built-in self- test (BIST) scheme. However, it still requires improvement in several aspects. This paper analyzes the limitation of OTM, and proposes new signature analysis scheme to improve its performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.9-16
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• 2004

For a System-on-a-Chip(SoC) comprised of multiple IP cores, test control techniques have been developed to perform the internal and external test efficiently relying on the various design for testability techniques such as scan and BIST(Built-In Self-Test). However the test area overhead is too expensive to guarantee diverse test link configurations. In this paper, at first we introduce a new flag based Wrapped Core Linking Module(WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores. Then a simple test control technique, which can interconnect internal scan chains of different cores, is described with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.

• Proceedings of the Korean Information Science Society Conference
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• 2006.06c
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• pp.241-243
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• 2006

소프트웨어의 재사용으로 인한 생산성 향상을 기대하면서, 컴포넌트 기반 개발(Component Based Development)에 관련한 연구가 지속적으로 이루어지고 있으며, 그 중 컴포넌트의 테스트 연구는 컴포넌트를 배포하고, 재사용하기 위해 검증하는데 기여하며 발전해 왔다. BIT(Built-In Test)와 컴포넌트 테스트를 위한 래퍼 클래스에 관한 연구가 대표적이다. 본 논문에서는 테스트 모듈의 산재를 방지하고, 유지보수성과 추적성 개선을 위해 테스트 프로세저를 모듈화하는 방안을 연구하였으며, 이를 위해 관점 지향 프로그래밍 개념을 도입하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.8 s.350
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• pp.27-34
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• 2006

During Built-In Self-Test(BIST), The set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns were undetected fault. In order to reduce the test time, we can remove useless patterns or change from them to useful patterns. In this paper, we reseed modify the pseudo-random and use an additional bit flag to improve test length and achieve high fault coverage. the fat that a random tset set contains useless patterns, so we present a technique, including both reseeding and bit modifying to remove useless patterns or change from them to useful patterns, and when the patterns change, we choose number of different less bit, leading to very short test length. the technique we present is applicable for single-stuck-at faults. the seeds we use are deterministic so 100% faults coverage can be achieve.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.72-82
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• 2014

Recently, the size of semiconductor industry market is constantly growing, due to the increase in diffusion of smart-phone, tablet PC and SSD(Solid State Drive). Also, it is expected that the demand for TLC NAND-type flash memory would gradually increase, with the recent release of TLC NAND-type flash memory in the SSD market. There have been a lot of studies on SLC NAND flash memory, but no research on TLC NAND flash memory has been conducted, yet. Also, a test of NAND-type flash memory is depending on a high-priced external equipment. Therefore, this study aims to suggest a structure for an autonomous test with no high-priced external test device by modifying the existing SLC NAND flash memory and MLC NAND flash memory test algorithms and patterns and applying them to TLC NAND flash memory.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.6
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• pp.284-292
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• 2008

The density of Memory has been increased by great challenge for memory technology; therefore, elements of memory become more smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. In addition, as the number of storage elements per chip increases, the test cost becomes more remarkable as the cost per transistor drops. Recent development in system-on-chip(SoC) technology makes it possible to incorporate large embedded memories into a chip. However, it also complicates the test process, since usually the embedded memories cannot be controlled from the external environment. We present a ARM processor-programmable built-in self-test(BIST) scheme suitable for embedded memory testing in the SoC environment. The proposed BIST circuit can be programmed vis an on-chip microprocessor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.526-531
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• 2003

Recently, many BIST(Built-in Self Test) schemes have been researched to reduce test time and hardware. But, most BIST schemes about pattern generation are for deterministic pattern generation. In this paper a new pseudo-random BIST scheme is provided to reduce the existing test hardware and keep a reasonable length of test time. Theoretical study demonstrates the possibility of the reduction of the hardware for pseudo-random test with some explanations and examples. Also the experimental results show that in the proposed test scheme the hardware for the pseudo-random test is much less than in the previous scheme and provide comparison of test time between the proposed scheme and the current one.

• The Journal of the Acoustical Society of Korea
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• v.18 no.1
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• pp.67-71
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• 1999

In this paper, we design circuits embedded in memory chip which perform memory testing algorithms using BIST scheme to reduce testing time and cost for testing. In order to implement circuits for MSCAN, Marching and checkerboard test algorithms, which have widely used in memory testing, we survey structure of the BIST circuits and describe each block of BIST circuits by using VHDL. Thereafter, We verify behavior of each VHDL coding block and extract BIST circuits for target testing algorithms by CAD tool for simulation and synthesis. Extracted circuits have very low area overhead.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.633-634
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• 2006

A new specification-based analog and mixed-signal test technique using high performance current sensors is proposed. The proposed technique using current sensors built in external ATE has little hardware overhead in circuit under test and high testability without time consuming operation of test point placement algorithm.

• The KIPS Transactions:PartD
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• v.10D no.2
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• pp.293-300
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• 2003

As Internet has grown rapidly and been more complex by technology in connection with Web and requirement of business, qualify and reliability of Web application are getting important. It is necessary to study about testing method along with design technique specially in Web application. This paper explains automation method of user interface test to make test cases about user input form with HTML pages using by built-in browser objects. Examples shows the possibility of testing automation with Javascript objects get mapped. Overhead of writing Javascript can be reduced by making script generator. Generated test scripts are repeatedly used in regression testing Web-based application.