• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.4
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• pp.3-10
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• 2007

In this paper, we proposed the methodology for security testing using block-based file fault injection. When fault is inserted into software, we consider the format of file in order to efficiently reduce the error that is caused by mismatch of format of file. The Vulnerability the methodology focuses on is related to memory processing, such as buffer overflow, null pointer reference and so on. We implemented the automatic tool to apply the methodology to image file format and named the tool ImageDigger. We executed fault-injection focused on WMF and EMF file format using ImageDigger, and found 10 DOS(Denial of Service) in Windows Platform. This methodology can apply to block-based file format such as MS Office file.

• Journal of Positioning, Navigation, and Timing
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• v.10 no.4
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• pp.315-333
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• 2021

Due to the Global Navigation Satellite System (GNSS) modernization, recently launched GNSS satellites transmit signals at various frequency bands such as L1, L2 and L5. Considering the Korean Positioning System (KPS) signal and other GNSS augmentation signals in the future, there is a high probability of applying more complex communication techniques to the new GNSS signals. For the reason, GNSS receivers based on flexible Software Defined Radio (SDR) concept needs to be developed to evaluate various experimental communication techniques by accessing each signal processing module in detail. This paper proposes a novel SDR-based A-GNSS receiver capable of processing multi-GNSS/RNSS signals at multi-frequency bands. Due to the modular structure, the proposed receiver has high flexibility and expandability. For real-time implementation, A-GNSS server software is designed to provide immediate delivery of satellite ephemeris data on demand. Due to the sampling bandwidth limitation of RF front-ends, multiple SDRs are considered to process the multi-GNSS/RNSS multi-frequency signals simultaneously. To avoid the overflow problem of sampled RF data, an efficient memory buffer management strategy was considered. To collect and process the multi-GNSS/RNSS multi-frequency signals in real-time, the proposed SDR A-GNSS receiver utilizes multiple threads implemented on a CPU and multiple NVIDIA CUDA GPGPUs for parallel processing. To evaluate the performance of the proposed SDR A-GNSS receiver, several experiments were performed with field collected data. By the experiments, it was shown that A-GNSS requirements can be satisfied sufficiently utilizing only milliseconds samples. The continuous signal tracking performance was also confirmed with the hundreds of milliseconds data for multi-GNSS/RNSS multi-frequency signals and with the ten-seconds data for multi-GNSS/RNSS single-frequency signals.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1113-1124
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel fur the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit of a field synchronized with the A/D converter. The implemented H/W used the 69%(16980) LAB(Logic Array Block) and 9%(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation of 60 fields/sec(30 frames/sec).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.8-13
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• 2001

Cerium oxide ($CeO_2$) thin film has been proposed as a buffer layer between the ferroelectric thin film and the Si substrate in Metal-Ferroelectric-Insulator-Silicon (MFIS) structures for ferroelectric random access memory (FRAM) applications. In this study, $CeO_2$ thin films were etched with $Cl_2$/Ar gas mixture in an inductively coupled plasma (ICP). Etch properties were measured for different gas mixing ratio of $Cl_2$($Cl_2$+Ar) while the other process conditions were fixed at RF power (600 W), dc bias voltage (-200 V), and chamber pressure (15 mTorr). The highest etch rate of $CeO_2$ thin film was 230 ${\AA}$/min and the selectivity of $CeO_2$ to $YMnO_3$ was 1.83 at $Cl_2$($Cl_2$+Ar gas mixing ratio of 0.2. The surface reaction of the etched $CeO_2$ thin films was investigated using x-ray photoelectron spectroscopy (XPS) analysis. There is a Ce-Cl bonding by chemical reaction between Ce and Cl. The results of secondary ion mass spectrometer (SIMS) analysis were compared with the results of XPS analysis and the Ce-Cl bonding was monitored at 176.15 (a.m.u). These results confirm that Ce atoms of $CeO_2$ thin films react with chlorine and a compound such as CeCl remains on the surface of etched $CeO_2$ thin films. These products can be removed by Ar ion bombardment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.71-76
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• 2008

H.264(or MPEG-4/AVC pt.10) is a high performance video coding standard, and is widely used. Variable length code (VLC) of the H.264 standard compresses data using the statistical distribution of values. A decoder parses the compressed bit stream and searches decoded values in lookup tables, and the decoding process is not easy to implement by hardware. We propose an architecture of variable length decoder(VLD) for the H.264 baseline profile(BP) L4. The CAVLD decodes syntax elements using the combination of arithmetic units and lookup tables for the optimized hardware architecture. A barral shifter and a first 1's detector parse NAL bit stream, and are shared by Exp-Golomb decoder and CAVLD. A FIFO memory between CAVLD and the reorder unit and a buffer at the output of the reorder unit eliminate the bottleneck of data stream. The proposed VLD is designed using Verilog-HDL and is implemented using an FPGA. The synthesis result using a 0.18um standard CMOS technology shows that the gate count is 22,604 and the decoder can process HD($1920{\times}1080$) video at 120MHz.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.5
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• pp.292-303
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• 2010

On-chip cache memories play an important role in both performance and energy consumption points of view in resource-constrained embedded systems by filtering many off-chip memory accesses. We propose a 2-level data cache architecture with a low energy-delay product tailored for the embedded systems. The L1 data cache is small and direct-mapped, and employs a write-through policy. In contrast, the L2 data cache is set-associative and adopts a write-back policy. Consequently, the L1 data cache is accessed in one cycle and is able to provide high cache bandwidth while the L2 data cache is effective in reducing global miss rate. To reduce the penalty of high miss rate caused by the small L1 cache and power consumption of address generation, we propose an ECP(Early Cache hit Predictor) scheme. The ECP predicts if the L1 cache has the requested data using both fast address generation and L1 cache hit prediction. To reduce high energy cost of accessing the L2 data cache due to heavy write-through traffic from the write buffer laid between the two cache levels, we propose a one-way write scheme. From our simulation-based experiments using a cycle-accurate simulator and embedded benchmarks, the proposed 2-level data cache architecture shows average 3.6% and 50% improvements in overall system performance and the data cache energy consumption.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.49 no.4
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• pp.17-22
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• 2012

Convolution filtering methods have been widely applied to various digital signal processing fields for image blurring, sharpening, edge detection, and noise reduction, etc. According to their application purpose, the filter mask size or shape and the mask value are selected in advance, and the designed filter is applied to input image for the convolution processing. In this paper, we proposed an image processing acceleration method for the convolution processing by using two-dimensional Look-up table (LUT) and overlap-region buffering technique. First, based on the fixed convolution mask value, the multiplication operation between 8 or 10 bit pixel values of the input image and the filter mask values is performed a priori, and the results memorized in LUT are referred during the convolution process. Second, based on symmetric structural characteristics of the convolution filters, inherent duplicated operation region is analysed, and the saved operation results in one step before in the predefined memory buffer is recalled and reused in current operation step. Through this buffering, unnecessary repeated filter operation on the same regions is minimized in sequential manner. As the proposed algorithms minimize the computational amount needed for the convolution operation, they work well under the operation environments utilizing embedded systems with limited computational resources or the environments of utilizing general personnel computers. A series of experiments under various situations verifies the effectiveness and usefulness of the proposed methods.

• Journal of KIISE:Databases
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• v.33 no.6
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• pp.563-577
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• 2006

A stream processor uses resource sharing method for efficient of limited resource in multiple continuous queries. The previous methods process aggregate queries to consist the level structure. So insert operation needs to reconstruct cost of the level structure. Also a search operation needs to search cost of aggregation information in each size of sliding windows. Therefore this paper uses linear structure for optimization of sliding window aggregations. The method comprises of making decision, generation and deletion of panes in sequence. The decision phase determines optimum pane size for holding accurate aggregate information. The generation phase stores aggregate information of data per pane from stream buffer. At the deletion phase, panes are deleted that are no longer used. The proposed method uses resources less than the method where level structures were used as data structures as it uses linear data format. The input cost of aggregate information is saved by calculating only pane size of data though numerous stream data is arrived, and the search cost of aggregate information is also saved by linear searching though those sliding window size is different each other. In experiment, the proposed method has low usage of memory and the speed of query processing is increased.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.271-274
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• 2014

This paper proposes high-performance SAO(Sample Adaptive Offset) in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. SAO is a newly adopted technique belonging to the in-loop filter in HEVC. The proposed SAO encoder hardware architecture uses three-layered buffers to minimize memory access time and to simplify pixel processing and also uses only adder, subtractor, shift register and feed-back comparator to reduce area. Furthermore, the proposed architecture consists of pipelined pixel classification and applying SAO parameters, and also classifies four consecutive pixels into EO and BO concurrently. These result in the reduction of processing time and computation. The proposed SAO encoder architecture is designed by Verilog HDL, and implemented by 180k logic gates in TSMC $0.18{\mu}m$ process. At 110MHz, the proposed SAO encoder can support 4K Ultra HD video encoding at 30fps in real time.