• 대한전기학회논문지:전력기술부문A
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• 제55권11호
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• pp.468-475
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• 2006

This paper reviews the energy characteristics of oil filled cables in transient state such as grounding fault and lightning surge. Artificial grounding fault test was firstly performed in 2003 for the analysis of arc voltage and breakdown energy according to the fault current. In this paper, energy of OF cable is variously analysed at joint box based on the actual test. Then more various conditions such as installation types, section lengths and CCPU(Cable Covering Protection Unit) connection types are applied for the simulation using EMTP when the single line to ground fault and direct lightning stroke are occurred on actual underground power cable systems and combined power cable systems, respectively. Finally, the energy by the length of crossbonded lead and grounding lead as well as fault lasting time is also calculated using EMTP simulation.

• 전기전자학회논문지
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• 제12권2호
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• pp.110-117
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• 2008

본 연구는 전력용 스위칭 소자로 널리 활용되고 있는 IGBT(Insulated Gate Bipolar Transistor)소자로서 NPT(Non Punch Through) IGBT 구조에 기반 한 새로운 구조의 IGBT를 제안하였다. 제안된 구조는 기존 IGBT 구조의 P-베이스 영역 우측 부분에 N+를 도입함으로 N-드리프트 영역의 정공분포를 N+영역으로 밀집시켜 턴-오프 시 정공의 흐름을 개선, 기존 구조보다 더 빠른 턴-오프 시간과 더 낮은 순방향 전압강하를 갖는 구조이다. 또한 P+를 게이트 우측 하단에 형성함으로써 순방향 전압 강하 특성을 개선시키기 위해 도입한 캐리어 축적 층인 N+에 의해 발생하는 낮은 래치-업 특성과 낮은 항복 전압 특성을 개선시킨 구조이다. 시뮬레이션 결과 제한된 구조의 턴-오프와 순방향 전압강하는 기존 구조대비 각각 0.3us, 0.5V 향상된 특성을 보였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.221-221
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• 2006

The SMD type P-N junction diode with ceramic package for diode case were fabricated. It was made this diode with simple process from $Al_2O_3$ ceramic chip, solder preform, diode chip, coating reagent and conductive paste for chip terrmination. Its merit is small size, easy manufacture. fast cooling with ceramic case. The electric characteristics of the diode such as reverse recovery time, breakdown voltage, forward voltage, and leakage current were 5 28ns, 1322V, 1.08V, $0.45{\mu}A$.

• 전기전자학회논문지
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• 제19권1호
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• pp.94-100
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• 2015

본 논문에서는 U-MOSFET 내부의 기생 body 다이오드(PN diode)를 쇼트키 body 다이오드(Schottky body diode)로 대체한 50V급 전력 U-MOSFET을 제안하였다. 쇼트키 다이오드는 PN 다이오드와 비교 시, 역 회복 손실(reverse recovery loss)을 감소시킬 수 있는 장점을 가지고 있다. 따라서 전력 MOSFET의 기생 body 다이오드를 쇼트키 body 다이오드를 대신함으로써 역 회복 손실을 최소화 할 수 있다. 제안된 쇼트키 body 다이오드(Schottky body diode) U-MOSFET(SU-MOS)를 conventional U-MOSFET(CU-MOS)와 전기적 특성을 비교한 결과, 전달(transfer) 및 출력(output)특성, 항복(breakdown)전압 등 정적(static) 특성의 변화 없이 감소된 역 회복 손실을 얻을 수 있었다. 즉, 쇼트키 다이오드의 폭(width)이 $0.2{\mu}m$, 쇼트키 장벽 높이(Schottky barrier height)가 0.8eV일 때 첨두 역전류(peak reverse current)는 21.09%, 역 회복 시간(reverse recovery time)은 7.68% 감소하였고, 성능지수(figure of merit(FOM))는 35% 향상되었다. 제안된 소자의 특성은 Synopsys사의 Sentaurus TCAD를 사용하여 분석되었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.652-654
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• 1993

In this paper, time variation properties of acoustic emission pulse were studied from low density polyethylene by using the self developed measuring system of aucoustic emission. When AC 15[kVrms] were applied to specimen of needle shape voids(0.5, 1.0, 1.5, 2.0[mm]), the breakdown time of void specimen was quite shorter than that of non-void specimen, thus the quick accurance of inception discharge were confirmed. It is observed that the skewness of the phase angle for applied voltage distribution phase, the average pulse of amplitude and the number of pulse are characteristic quantity of discharge.

• 전기전자학회논문지
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• 제20권3호
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• pp.295-298
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• 2016

본 논문에서는 기존 ESD 보호소자인 SCR과 MVSCR, LVTSCR의 Turn-on-Time 및 전기적 특성을 시놉시스사의 T-Cad 시뮬레이션을 통하여 분석하였다. 분석결과 세 소자 모두 대략 2V 에서 3V 내외의 홀딩전압 특성을 보였으며, SCR은 약 20V의, MVSCR은 약 12V, LVTSCR은 9V로 순차적으로 개선된 트리거 특성을 보였다. 턴-온타임 시뮬레이션 결과는 SCR이 2.8ns, MVSCR과 LVTSCR은 각각 2.2ns, 2.0ns로 LVTSCR이 가장 짧은 턴-온 특성을 보였다. 반면 IT2 는 SCR이 약 7.7A, MVSCR은 5.5A LVTSCR은 4A의 특성을 보였으므로 I/O 및 파워 클램프 단에 적용 시 동작전압에 따른 최적화된 소자를 선택해야 한다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.131-131
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• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility ($\sim900cm^2/Vs$). These electronic properties allow high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances, the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. This paper studies different channel dimensons ($L_{CH}$ : $0.5{\mu}m$, $1\;{\mu}m$, $1.5\;{\mu}m$) and their effect on the the device transient characteristics. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship. with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. We observe an increase in the turn-on and turn-off time with increasing the channel length. The switching time in 4H-SiC DMOSFETs have been found to be seriously affected by the various intrinsic parasitic components, such as gate-source capacitance and channel resistance. The intrinsic parasitic components relate to the delay time required for the carrier transit from source to drain. Therefore, improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.55-55
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• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility (${\sim}900cm^2/Vs$). These electronic properties allow high breakdown voltage, high frequency, and high temperature operation compared to Silicon devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances. the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. In this paper, we report the effect of the interface states ($Q_s$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. The result is a low-loss transient characteristic at low $Q_s$. Based on the simulation results, the DMOSFETs exhibit the turn-on time of 10ns at short channel and 9ns at without the interface charges. By reducing $SiO_2/SiC$ interface charge, power losses and switching time also decreases, primarily due to the lowered channel mobilities. As high density interface states can result in increased carrier trapping, or recombination centers or scattering sites. Therefore, the quality of $SiO_2/SiC$ interfaces is important for both static and transient properties of SiC MOSFET devices.