• Journal of KIISE:Software and Applications
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• v.34 no.8
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• pp.743-751
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• 2007

Model checking has been successfully applied to hardware verification. Software is more subtle than hardware with respect to formal verification due to its infinite state space. Although there are many research activities in this area, bounded model checking is regarded as a promising technique. Bounded model checking uses an upper bound to unroll its model, which is the main advantage of bounded model checking compared to other model checking techniques. In this paper, we applied bounded model checking to verify BIR which is the input model for the model checking tool BOGOR. Some BIR examples are verified with our technique. Experimental results show that bounded model checking is better than explicit model checking provided by BOGOR. This paper presents the formalization of BIR and the encoding algorithm of BIR into CNF.

• Journal of KIISE:Software and Applications
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• v.35 no.9
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• pp.529-537
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• 2008

Since concurrent software is hard to debug, the verification of such systems inevitably needs automatic tools which support exhaustive searching. Bounded Model Checking (BMC) is one of them. Within a bound k, BMC exhaustively check some errors in execution traces of the given system. In this paper, we introduce the tool that performs BMC for LTS, modeling language for concurrent programs. In this tool, a property is described by a FLTL formula, which is suitable to present the property with actions in a LTS model. To experiment with existential model checkers and out tool, we compare and analysis the performance of the developed tool and others.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.2
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• pp.1-10
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• 1999

Direct extraction of FET's small signal model parameters needs predetermined parasitic elements usually obtained under forward cold FET conditionl This paper derives analytic intrinsic model for cold FET's and shows that normal cold FET condition can replace forward cold FET condition for extracting parasitic elements. Then, we track the error of hot FET's small signal model bounded by the cold FET condition and examine the validness of cold parasitic resistances by checking the existence of the error minimum.